Inspection pattern, inspection method, and inspection system...

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

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Details

C438S622000, C438S625000, C438S017000

Reexamination Certificate

active

06884637

ABSTRACT:
An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact chain, and electrode terminals. The inspection method includes the steps of acquiring an applied-voltage versus measured-current characteristic or an elapsed-time versus measured-voltage characteristic of the inspection pattern, and judging presence or absence of a latent defect of the inspection pattern on the basis of the acquired characteristic. The inspection system includes a voltage-applying/current-measuring device or a constant-current-feeding/voltage-measuring device, and a judging device for judging presence or absence of a latent defect of the inspection pattern.

REFERENCES:
patent: 5900735 (1999-05-01), Yamamoto
patent: 10-135297 (1998-05-01), None
patent: 10135297 (1998-05-01), None
patent: 10-135298 (1998-05-01), None
patent: 10-341079 (1998-12-01), None
patent: 2000-232144 (2000-08-01), None

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