Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-07-15
2002-07-02
Maung, Zarni (Department: 2154)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S028000, C717S152000, C712S227000
Reexamination Certificate
active
06415393
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit device comprising at least a central processing unit, a bus control circuit, and an inspection control circuit, and a method and an apparatus for inspecting such an integrated circuit device.
2. Description of the Related Art
Heretofore, a system called an ICE (In-Circuit Emulator) has been used to inspect internal operations of integrated circuit devices constructed as single chips. The ICE system reads all input and output signals of an integrated circuit device to emulate internal operations thereof. Therefore, the ICE system is capable of debugging an integrated circuit device while it is in a development stage.
The ICE system is required to connect its connection terminals individually to all the input and output terminals of an integrated circuit device to be inspected, therefore it is difficult to use the ICE system to inspect an integrated circuit device when it is mounted on a circuit board. To eliminate such a drawback, there has been proposed an integrated circuit device incorporating a built-in inspection control circuit which is capable of debugging the integrated circuit device while it is mounted on a circuit board.
One conventional integrated circuit device with such a built-in inspection control circuit will be described below with reference to
FIG. 1
of the accompanying drawings.
FIG. 1
shows in block form an internal structure of a conventional integrated circuit device. As shown in
FIG. 1
, the integrated circuit device, generally designated by
100
, has a CPU (Central Processing Unit) core
1
connected by a dedicated internal bus
2
to a BCU (Bus Control Unit)
3
which is connected to a main bus
4
.
The integrated circuit device
100
also has various peripheral circuits
5
connected to the main bus
4
. A number of lead terminals
7
are connected through the main bus
4
to the CPU core
1
, the BCU
3
, and the peripheral circuits
5
. The integrated circuit device
100
further includes a DCU (Debug Control Unit)
6
as an inspection control circuit independent of the main bus
4
. The DCU
6
has a plurality of boundary scan cells
8
connected respectively to a plurality of lead terminals
10
serving as an inspection information I/F (Interface)
9
of JTAG (Joint Test Action Group).
Boundary scan cells
8
are also connected individually to the lead terminals
7
. The boundary scan cells
8
connected to the lead terminals
7
are connected in a loop pattern from one of the boundary scan cells
8
of the DCU
6
to the other boundary scan cell
8
of the DCU
6
.
The integrated circuit device
100
of the above structure, even when it is mounted on a circuit board (not shown) desired by the user, can be debugged by a boundary scan test. For debugging the integrated circuit device
100
, a debugging connector is mounted on the circuit board, and the inspection information I/F
9
of the integrated circuit device
100
mounted on the circuit board is connected to the debugging connector.
The lead terminals
7
other than the inspection information I/F
9
of the integrated circuit device
100
are connected respectively to necessary leads on the circuit board. When an ordinary mode is established as an operation mode of the integrated circuit device
100
, since the boundary scan cells
8
connected individually to the lead terminals
7
pass communication data without changing it, the CPU core
1
, etc. of the integrated circuit device
100
can communicate with the leads on the circuit board through the lead terminals
7
.
When the connector of a circuit inspection device (not shown) is connected to the connector on the circuit board and the operation mode of the integrated circuit device
100
is switched to a test mode, bus cycles of the CPU core
1
are stopped at a certain time, and the boundary scan cells
8
form a shift register.
Now, communication data including addresses and commands which the CPU core
1
, etc. communicate through the lead terminals
7
can be replaced and acquired by the DCU
6
through the shift register made up of the boundary scan cells
8
. Because the boundary scan cells
8
are connected to the circuit inspection device through the inspection information I/F
9
, the circuit inspection device can inspect internal operations of the integrated circuit device
100
.
Another conventional integrated circuit device with such a built-in inspection control circuit will be described below with reference to
FIG. 2
of the accompanying drawings.
FIG. 2
shows in block form an internal structure of the integrated circuit device. Those parts shown in
FIG. 2
which are identical to those of the conventional integrated circuit device shown in
FIG. 1
are identically referred to, and will not be described in detail below.
The integrated circuit device, generally designated by
200
, has a CPU core
21
connected by a dedicated internal bus
22
to a BCU
23
which is connected to a main bus
24
. To the main bus
24
, there are connected various peripheral circuits
25
and a DCU
26
as an inspection control circuit. A number of lead terminals
27
are connected through the main bus
24
to the CPU core
21
, the BCU
23
, and the peripheral circuits
25
.
Unlike the integrated circuit device
100
, the DCU
26
has a DMA (Direct Memory Access) controller
28
that is directly connected to the main bus
24
. To the DCU
26
, there are connected a plurality of lead terminals
30
as an inspection information I/F
29
of JTAG, which are connected to the DMA controller
28
.
The DCU
26
has no boundary scan cells, and the lead terminals
27
have no boundary scan cells either. Various I/O (Input/Output) ports
31
and a memory
32
as an information storage medium on a circuit board (not shown) are connected to the lead terminals
27
which are connected directly to the BCU
23
. The memory
32
stores, for example, instruction codes and processed data which are to be read by the integrated circuit device
200
.
A debugging connector is mounted on a circuit board prepared by the user, and the inspection information I/F
29
of the integrated circuit device
200
mounted on the circuit board is connected to the debugging connector. In an ordinary mode, data communications with the peripheral circuits
25
through the main bus
24
are controlled by the CPU core
21
through the BCU
23
.
When the connector of a circuit inspection device (not shown) is connected to the connector on the circuit board and a test mode is started for the integrated circuit device
200
, the DCU
26
can directly access the peripheral circuits
25
from the main bus
24
without being routed through the BCU
23
due to a DMA function of the DMA controller
28
. Therefore, the circuit inspection device can inspect internal operations of the integrated circuit device
200
.
Consequently, the integrated circuit devices
100
,
200
can be inspected for their internal operations while being mounted on the circuit board that the user has prepared.
However, the integrated circuit device
100
with the boundary scan cells cannot easily be controlled because bus cycles of the CPU core
1
need to be stopped at an appropriate time for inspecting internal operations of the integrated circuit device
100
, and communication data is replaced and acquired through the shift register made up of the boundary scan cells
8
.
Because the boundary scan cells
8
which make up the shift register need to be connected individually to the lead terminals
7
, the integrated circuit device
100
is relatively complex in structure and large in size. The boundary scan cells
8
connected individually to the lead terminals
7
can basically be used only for the boundary cell test, and hence are not highly versatile in nature.
With the integrated circuit device
200
based on the DMA principles, the DCU
26
directly accesses the peripheral circuits
25
and the BCU
23
without being routed through the CPU core
21
due to a DMA function of the DMA controller
Lin Wen-Tai
Maung Zarni
McGinn & Gibb PLLC
NEC Corporation
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