Inspection method for semiconductor memory

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – For fault location

Reexamination Certificate

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C324S211000, C324S527000

Reexamination Certificate

active

07982466

ABSTRACT:
A method for inspecting a semiconductor memory having nonvolatile memory cells using ferroelectric capacitors is disclosed which comprises, after shelf-aging the ferroelectric capacitor in a first polarized state, the steps of: (a) writing a second polarized state opposite to the first polarized state; (b) shelf-aging the ferroelectric capacitor in the second polarized state; and (c) reading the second polarized state. The temperature or voltage in the step (a) is lower than the temperature or voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time.

REFERENCES:
patent: 5086412 (1992-02-01), Jaffe et al.
patent: 5337279 (1994-08-01), Gregory et al.
patent: 5432731 (1995-07-01), Kirsch et al.
patent: 5677865 (1997-10-01), Seyyedy
patent: 5953619 (1999-09-01), Miyazawa et al.
patent: 6008659 (1999-12-01), Traynor
patent: 6038160 (2000-03-01), Nakane et al.
patent: 6335876 (2002-01-01), Shuto
patent: 6358758 (2002-03-01), Arita et al.
patent: 6388913 (2002-05-01), Kuo et al.
patent: 6735546 (2004-05-01), Scheuerlein
patent: 6878980 (2005-04-01), Gudesen et al.
patent: 6898104 (2005-05-01), Ogiwara et al.
patent: 6928376 (2005-08-01), Rodriguez et al.
patent: 7085150 (2006-08-01), Rodriguez et al.
patent: 7148530 (2006-12-01), Shin et al.
patent: 7768811 (2010-08-01), Matsuno et al.
patent: 2007/0211512 (2007-09-01), Shuto
patent: 11-102600 (1999-04-01), None
patent: 2001-67896 (2001-03-01), None
patent: 2002-8397 (2002-01-01), None
Tetsuro, Machine Translation of JP 11-102600, Feb. 15, 2008, JPO.
Tetsuro JP 1999-102600 (JP 11-102600) English translation by USPTO, McElroy Translation Company, Mar. 2008, p. 1-32.
International Search Report of PCT/JP2004/007962 date of mailing Mar. 22, 2005.

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