Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
2002-09-12
2004-09-28
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
C702S083000, C714S724000, C714S733000, C438S010000, C438S012000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06799130
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an inspection method used in a production process of an electronic device such as a semiconductor integrated circuit, and relates to an inspection apparatus or inspection tool and an inspection system, which are used for realizing the inspection method, and a manufacturing method of a semiconductor device.
In the production of an electronic device typified by a semiconductor integrated circuit, after a defect is detected by darkfield and brightfield inspection tools, the detected defect is often reviewed in order to analyze an individual detected defect using a defect review function provided in the inspection tool itself or a dedicated image acquiring tool, such as a review apparatus or review tool, having an electron microscope, etc.
It is to be noted that the darkfield inspection tool detects a particle adhered to a wafer whereas the brightfield inspection tool detects a particle and a pattern defect formed on the wafer. Hereinafter the particle and the pattern defect are generically referred to as defect.
As compared with the darkfield and brightfield inspection tools, the review tool picks up a position of an individual defect as a high-resolution image. Accordingly, the review tool does not pick up all defect positions detected by the inspection tool, but samples the defect positions on a surface of a wafer to limit the number of defect positions to a few before picking up an image.
Conventionally, random sampling was used for the above-mentioned sampling; more specifically, a defect was selected at random from among the detected defects.
In addition, Japanese Patent Laid-open No. Hei 10-214866 discloses a technology in which, if there is a cluster-like defect such as a flaw or closely formed defects, classifying defects detected by an inspection tool into defects inside the cluster-like defect and defects outside the cluster-like defect. Even in such a case, a few defects are sampled at random from among the defects inside the cluster-like defect; and likewise, a few defects are sampled at random from among the defects outside the cluster-like defect.
Although it was possible to grasp statistically a tendency of defects using the conventional random sampling, a necessary defect was not efficiently reviewed. For example, measures could not be taken by priority against a critical defect causing an electrical failure; with the result that it was difficult to improve a yield effectively.
Moreover, with the microminiaturization of a circuit pattern of a semiconductor, the size of a detectable defect, required for an inspection tool, becomes smaller. For this reason, performance of the inspection tool is being enhanced accordingly, leading to an increase in the number of defects to be detected. Therefore, establishment of an effective reviewing method is desired.
SUMMARY OF THE INVENTION
The present invention provides an inspection method that can judge a defect which should be reviewed by priority so as to improve efficiency in inspection, and also provides a tool therefor.
Further, the present invention provides a manufacturing method of a semiconductor device that can take measures against a failure efficiently to improve a yield of the semiconductor device by judging a defect which should be reviewed by priority so as to improve efficiency in inspection.
To be more specific, the present invention is characterized in that paying attention to the relation between a defect size and a layout of a LSI chip, or the relation between a defect and a wiring pattern, a defect which should be reviewed by priority is select.
FIG. 9
illustrates a positional distribution of defects in a chip observed after an inspection tool detects the defects.
In this figure, data
35
of the defects detected by the inspection tool is plotted on a schematic diagram
32
illustrating a design circuit layout of the LSI chip. To be more specific, the detected defects are plotted according to position coordinates in respective LSI chips on a wafer. Each black dot indicates an individual defect. Rectangular frames B
1
through B
7
indicate positions of LSI block
1
through LSI block
7
, respectively. Here, the LSI blocks include, for example, an A/D conversion block, a D/A conversion block, a memory block, and a processor block if the LSI blocks relate to a LSI used for a cellular phone. The LSI block is called a circuit block in general. Each LSI block has an independent function inside a LSI, and its placement also differs from the other except wiring connections.
As shown in the figure, the distribution of the defects detected by the inspection tool closely relates to a circuit layout, and has the following tendencies:
(1) The defect density differs according to roughness and fineness of a circuit layout. Depending on a kind of the inspection tool, the number of defects detected in an area where a circuit layout is rough is greater than the number of defects detected in an area where a circuit layout is fine. In general, roughness and fineness of circuit patterns differ on a LSI block basis; for example, a wiring width of a processor block is narrower than that of a memory block. Therefore, if a layout becomes dense, the inspection tool detects more defects in the processor block in comparison with the memory block.
(2) At edges (outlines) of the LSI block in the circuit layout, many defects are detected. The reason why this phenomenon occurs is that the inspection tool often detects a defect which is not a real defect by mistake. The inspection tool tends to detect such a false defect in a portion where a difference in unevenness of circuit patterns is large. In this case, an edge (outline) is a border between circuit blocks, and has a width ranging from tens to hundreds of micrometers.
In view of the foregoing, according to the present invention, a defect to be reviewed is selected using a LSI design layout in order to achieve the above-mentioned purpose. To be more specific, a defect which is not close to LSI block outlines is reviewed by priority using LSI design layout information; and a defect in a LSI block, a wiring width of which is narrow, is reviewed by priority.
Moreover, as shown in
FIG. 11
, it is also possible to judge the criticality of a defect with higher accuracy by using a wiring pattern image as a substitute for the design layout information to examine directly the relation between the wiring pattern image and the defect in detail.
This permits a defect which has a high possibility of influencing a yield to be efficiently reviewed by priority, whereby a direct factor exerting the influence can be identified in a short period of time and measures against the factor can easily be taken. Consequently, time taken to produce a defective unit is shortened, which leads to improvement in yield.
As is the case with a system LSI in particular, for a LSI item in which various circuit blocks exist, judging a defect which should be reviewed by priority is essential to an early improvement in yield.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 6185707 (2001-02-01), Smith et al.
patent: 6456951 (2002-09-01), Maeda et al.
patent: 2002/0052053 (2002-05-01), Ono et al.
patent: 2003/0093767 (2003-05-01), Murai et al.
patent: 2003/0195712 (2003-10-01), Ono et al.
Maeda Shunji
Okabe Takafumi
Sakai Kaoru
Antonelli Terry Stout & Kraus LLP
Barlow John
Bhat Aditiya
Hitachi , Ltd.
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