Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Reexamination Certificate
2000-08-25
2003-01-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
Reexamination Certificate
active
06509197
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of inspection and analysis of specimens and, more particularly, to defect inspection and analysis of semiconductor integrated circuits.
2. Description of the Prior Art
In the semiconductor integrated circuit (IC) industry, there is a continuing demand for higher circuit packing densities. This demand of increased packing densities has led the semiconductor industry to develop new materials and processes to achieve sub-micron device dimensions. Manufacturing IC's at such minute dimensions adds more complexity to circuits and the demand for improved methods to inspect integrated circuits in various stages of their manufacture is ever present.
Although inspection of such products at various stages of manufacture is very important and can significantly improve production yield and product reliability, the increased complexity of IC's increases the cost of such inspections, both in terms of expense and time. However, if a defect can be detected early in production, the cause of the defect can be determined and corrected before a significant number of defective IC's are manufactured.
In order to overcome the problems posed by defective IC's, IC manufacturers sometimes fabricate semiconductor defect test structures. Such defect test structures are dedicated to defect analysis. The defect test structures are fabricated such that they are sensitive to defects that occur in IC product, but are designed so that the presence of defects is more readily ascertained. Such defect test structures are often constructed on the same semiconductor substrate as the IC products.
One example of a defect test structure is found in the Copper CMP Test Mask Set designed at MIT. This test mask set is designed to quantify the dependence of the resulting copper line profile on parameters such as line pitch, line width and line aspect ratio. However, the MIT mask set is designed to be probed using conventional electrical testing in which current is passed through the device by contacting predefined pad of large area (approximately 100×100 &mgr;m
2
) with electrical probes, not by electron beam. As is well known in the art, defect detecting systems frequently utilize charged particle beams. In such systems, a charged particle beam, such as an electron beam, is irradiated on defect test structures. The interaction of the electron beam with features in the circuitry generates a number of signals in varying intensities, such as secondary electrons, back-scattered electrons, x-rays, etc. Typically, electron beam methods employ secondary electron signals for the well known “voltage contrast” technique for circuit defect detection.
The voltage contrast technique operates on the basis that potential differences in the various locations of a test structure under examination cause differences in secondary electron emission intensities. Thus, the potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
A secondary electron detector is used to measure the intensity of the secondary electron emission that originates only at the path swept by the scanning electron beam. A defective portion can be identified from the potential state of the portion under inspection. In one form of inspection, the mismatched portion between the defective voltage contrast image and the defect free one reveals the defect location.
Thus, in such systems, the voltage contrast is simultaneously monitored for both defective and defect free circuits for each circuit manufactured. However, considering the density of IC's currently produced, the time necessary to scan voltage contrast data to perform comparisons is significant. The inspection and analysis of such circuits may take several days. Accordingly, more efficient voltage contrast inspection systems are desirable.
SUMMARY
The present invention includes a system for detecting defects in test structures. The system operates so as to provide efficient and effective testing of defects. It also includes novel test structures that provide for improved defect testing, as are described more fully below.
In one embodiment, a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die is disclosed. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.
In another aspect, the invention pertains to a method of testing a semiconductor die. The semiconductor die has a substrate, a first metal layer and a second metal layer formed over the first metal layer. A first metal test structure is formed in the first metal layer of the semiconductor die such that the first metal test structure has a first electrical connection. A second metal test structure is formed in the second metal layer of the semiconductor die such that the second metal test structure has a second electrical connection to the first metal test structure. The second electrical connection is formed at a distance from the first electrical connection. It is determined whether the first metal test structure is intact between the first electrical connection and the second electrical connection by evaluating the extent electrical current can pass from the second metal test structure to the first connection.
In another aspect, a method of fabricating a test structure is disclosed. A voltage contrast test structure element is formed, and at least one nonconductive layer is formed over at least a portion of the test structure element. At least one conductive element is formed within the nonconductive layer. The conductive element is electrically coupled with voltage contrast test structure.
In another embodiment, a method of verifying quality of a product is disclosed. Data concerning product quality that was produced by subjecting voltage contrast test structures present on the product to voltage contrast testing during manufacturing of the product is obtained. At least a portion of voltage contrast structures present on the product are re-inspected prior to product acceptance thereby producing additional data representing product quality.
In another aspect, a semiconductor die is disclosed. The die includes a lower test structure element, a nonconductive layer over at least a portion of the lower test structure element, an upper test structure element at a higher level than at least a portion of the lower test structure element, and a conductive element within the nonconductive layer. The conductive element is electrically coupled with the lower test structure element and the upper test structure element. Preferably, the semiconductor die further includes a plurality of lower test structure elements and a plurality of upper test structure elements. The lower test structure elements are formed within a same first conductive laye
Long Robert Thomas
Mantalas Lynda C.
Pinto Gustavo A.
Richardson Neil
Satya Akella V. S.
Beyer Weaver & Thomas LLP
KLA-Tencor Corporation
Niebling John F.
Stevenson Andre' C
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