Insertion of spare logic gates into the unused spaces...

Details Insertion of spare logic gates into the unused spaces... Insertion of spare logic gates into the unused spaces...

1999-07-01

2001-11-20

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06321371

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits, and more particularly, to a method and apparatus for inserting spare logic gates into the unused spaces between individual gates in standard cell artwork.
BACKGROUND OF THE INVENTION
Electronic devices including computers, televisions, and telephones require integrated circuits to operate. An integrated circuit (IC) is an interconnected array of active and passive electronic elements, such as transistors and resistors, formed on a semiconductor substrate and generally housed in a plastic or ceramic package. Electrical connectors or pins pass through the package to connect the integrated circuit with an external electrical circuit.
As electronic devices become faster, smaller, and perform more complex functions, the integrated circuits likewise become more complex. It is extremely difficult to design a very complex integrated circuit, which may include millions of transistors and run at hundreds of megahertz, or hundreds of millions of cycles each second. The logic, or functional design, of the integrated circuit is first produced, then a network of logic gates is planned to implement the logic design. A logic gate is typically a small block of transistors and other circuit elements, grouped to perform a certain logic operation. The resulting network of logic gates is generally described in a netlist, a list of logic gates and their interconnections which implement the logic design, but which usually does not describe the physical layout of the circuit.
A place and route software tool is generally used to create the physical layout, or artwork, of the integrated circuit from the netlist. The place and route software requires a library file containing a set of predefined logic cells or blocks to implement the network of logic gates defined in the netlist. Each logic cell may contain the physical description of power and ground conductors and the field effect transistors (fets) needed to form one or more logic gates.
Typical place and route software first places all logic cells in a stack in the center of the circuit area. The logic cells are then moved apart by the software to resolve overlaps. The software then performs a global routing operation, in which the logic cells are further moved apart to allow room for routing wires between the logic cells, without actually placing any wires. Most place and route software moves the logic cells apart by placing spacer cells between the logic cells, where a spacer cell (logic-free) contains some minimal routing for power and ground, and possibly one or more bypass capacitors between the power and ground wires. A routing operation then places the electrical wires, or electrical routing, in one or more layers between the logic cells according to the netlist.
Referring now to
FIG. 1
, a logic-free spacer cell
10
may be formed on a silicon wafer in a standard CMOS process. Basically, a CMOS integrated circuit is formed on the silicon wafer in a series of levels or steps, including n-well (e.g.,
20
), n-well active (e.g.,
22
), non n-well active (e.g.,
24
), polysilicon (polycrystalline silicon) (e.g.,
16
), and metal (e.g.,
12
and
14
), with connections from active to polysilicon (e.g.,
26
and
34
) and from polysilicon to metal (e.g.,
30
and
32
). The intersections between polysilicon traces and n-well active form pfets (p-type field effect transistors), and the intersections between polysilicon traces and non n-well active form nfets (n-type fets).
The logic-free spacer cell
10
comprises a power conductor
12
, a ground conductor
14
, and a bypass capacitor
16
. Power
12
and ground
14
are formed in the metal layer of the integrated circuit, with an n-well
20
formed at the top of the cell
10
. An n-well active region
22
underlies power
12
inside the n-well
20
, and a non n-well active region
24
underlies ground
14
. The bypass capacitor
16
comprises a very large fet formed in the polysilicon, or poly, layer over gate oxide which acts as a dielectric for the capacitor between power
12
and ground
14
. The n-well active region
22
is connected to power
12
with several connectors
26
and
28
. The poly bypass capacitor
16
is connected to power
12
with several connectors
30
and
32
. The non n-well active region
24
is connected to ground
14
by several connectors
34
,
36
, and
38
. The capacitance between power
12
and ground
14
helps prevent power spikes or fluctuations in the integrated circuit, but does not perform any logic functions in the circuit.
As an integrated circuit is designed, its operation is simulated on a computer to try to find logic faults. An integrated circuit is usually simulated both at the netlist stage and after a physical layout has been created. However, fully simulating every possible state of a complex integrated circuit is virtually impossible. The circuit designer and tester create a test that is as nearly complete as possible under time and budget constraints, but fully simulating every possible state in an integrated circuit would be expensive, if even possible. Furthermore, simulators may not reproduce all faults caused by the physical layout of the circuit. For example, the design logic of a circuit may be correct, but if two high-speed electrical wires are placed too closely together, they may be coupled by electromagnetic fields. That is, a signal on one wire may induce a signal to appear on the other, resulting in errors during operation of the integrated circuit. Functional tests on a fabricated integrated circuit are therefore used to supplement simulations.
Faults in the design logic or in the physical layout of a very complex integrated circuit are very common the first time the circuit is fabricated. Designers and fabricators of integrated circuits have several methods of correcting these faults without completely redesigning the physical layout. An integrated circuit is fabricated in a series of steps, forming the logic gates (made up of transistors) and other elements on a semiconductor substrate first, then forming multiple layers of routing interconnecting the transistors and other elements. By including spare logic gates in the original artwork, logic changes can be made by altering the routing, leaving the placement of the logic gates unchanged.
In one method for including spare logic gates, a “fet-farm” is created, in which an area is created outside the standard cell artwork containing an array or “farm” of fets, or transistors. The standard cell artwork consists of the logic and spacer cells and routing needed to implement the netlist.
The fets in the fet-farm are “tied down,” or connected to power and/or ground so as to hold them in a given state, preventing them from randomly fluctuating or floating. This solution has a significant disadvantage in that few routing resources remain in the standard cell artwork allowing fets in the farm to be connected to cells within the standard cell artwork. The place and route operation attempts to place logic cells as closely as possible within the circuit in order to minimize the size of the circuit and increase the maximum operating speed of the circuit. This reduces the area left in the artwork available for placing new routing. Furthermore, fet-farms limit the speed of the circuit, since a signal must travel an undesirably large distance across the circuit between the farm and logic cells deep in the circuit. Finally, a fet-farm increases the size of an integrated circuit.
In another method for including spare logic gates, known as “happy-gates,” spare logic gates are specifically added to the integrated circuit by the designer so that they appear in the netlist. The standard place and route software then places the happy-gate logic cells corresponding to the spare logic gates into the standard cell artwork, making them somewhat more accessible to standard cells than in the fet-farm technique. Thus the place and route software places the original logic cells, the happy-gate logic cells, and the

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