Insertion of repeaters without timing constraints

Details Insertion of repeaters without timing constraints Insertion of repeaters without timing constraints

2006-03-07

2006-03-07

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07010767

ABSTRACT:
A method/process for repeater insertion in the absence of timing constraints. Delays are optimized for multi-receiver and multi-layer nets and can be introduced in the early steps of design planning. It serves as a tool for interconnect prediction as well as planning. In the presented formulation, no restrictions are made on where the repeaters are added or what the topology of the net is. The tabulated results demonstrate improvement (speed ups) using the method/process of the present invention. The present invention runs in linear time and achieves better results that the existing dynamic programming formulation and other published heuristics. Polarity in a circuit design is corrected by traversing the circuit and carrying backwards a cost of fixing the polarity. On a subsequent traversal, buffers inserted fix the polarity.

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