Input termination for delay locked loop feedback with...

Details Input termination for delay locked loop feedback with... Input termination for delay locked loop feedback with...

2011-03-01

2011-03-01

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

Reexamination Certificate

active

07898288

ABSTRACT:
A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.

REFERENCES:
patent: 5760610 (1998-06-01), Naffziger
patent: 6812754 (2004-11-01), Nakanishi
patent: 2003/0001618 (2003-01-01), Haycock et al.

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