Input stage using junction field effect transistors for biasing

Details Input stage using junction field effect transistors for biasing Input stage using junction field effect transistors for biasing

1979-09-13

1982-02-16

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307571, 307304, H03K 1700, H03K 17687

Patent

active

043161022

ABSTRACT:
In a bias circuit including at least a pair of bipolar transistors interconnected to function as active loads, two junction field effect transistors are interconnected such that the source of one transistor is connected to the emitter of the first of the pair of bipolar transistors and the source of the second junction field effect transistor is connected to the emitter of the second of said bipolar transistors, and the gate electrodes of the first and second junction field effect transistors are electrically connected to each other and to the drain electrodes of both the first and second junction field effect transistors. Alternatively, the drain electrodes of the first and second junction field effect transistors are connected to a common bus and the gate electrodes are connected to a low impedance node.

REFERENCES:
patent: 3732442 (1973-05-01), Husbands et al.
patent: 3947778 (1976-03-01), Hsiao et al.
patent: 3961279 (1976-06-01), Davis
patent: 4194136 (1980-03-01), Butler
RCA Tech Notes, Hybrid B. Por. and Mos. Flip-Flop Circuits by S. Katz, RCA TN No. 683, 6/66.
IBM Tech. Dsclre. Bulletin, Monolithic Memory Cell with Junction FET Loads, S. Wiedmann, vol. 13, No. 2, 7/70.

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