Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2011-06-28
2011-06-28
Cho, James (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000
Reexamination Certificate
active
07969190
ABSTRACT:
A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.
REFERENCES:
patent: 4825106 (1989-04-01), Tipon et al.
patent: 5311073 (1994-05-01), Dallavalle
patent: 5319259 (1994-06-01), Merrill
patent: 5378945 (1995-01-01), Partovi et al.
patent: 5495185 (1996-02-01), Goto
patent: 5515319 (1996-05-01), Smayling et al.
patent: 5521531 (1996-05-01), Okuzumi
patent: 5541534 (1996-07-01), Cao et al.
patent: 5646809 (1997-07-01), Motley et al.
patent: 5663659 (1997-09-01), Kaminaga et al.
patent: 5680063 (1997-10-01), Ludwig et al.
patent: 5744982 (1998-04-01), Chu
patent: 5867010 (1999-02-01), Hinedi et al.
patent: 5880605 (1999-03-01), McManus
patent: 6163179 (2000-12-01), Huang et al.
patent: 6225838 (2001-05-01), Lee
patent: 6255850 (2001-07-01), Turner
J. Williams, “Mixing 3V and 5V ICs,” IEEE Spectrum, vol. 30, No. 3, pp. 40-42, Mar. 1993.
International Technology Roadmap for Semiconductors 2002 Update, Semiconductor Industry Association.
Sedra, Adel S., Microelectronic Circuits, 1998, Oxford University Press, pp. 366, 374-375.
Chuang Che-Hao
Ker Ming-Dou
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