Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-03-23
2003-03-11
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S230010
Reexamination Certificate
active
06532179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor integrated circuit which has receiving circuits for receiving input signals supplied from exterior in synchronization with a timing signal such as a clock signal.
2. Description of the Related Art
FIG. 1
shows the essential parts of a semiconductor integrated circuit having a receiving circuit of this type.
This semiconductor integrated circuit is formed, for example, as a DRAM. The DRAM has a plurality of pads
2
, input circuits
4
connected to these pads
2
, and a latching circuit
6
. Aside from the parts shown in the diagram, the DRAM also includes pads for control signals and data signals, control circuits, memory cell arrays, and so on. The pads
2
are respectively supplied with a clock signal CLK and address signals ADD
0
-ADD
5
from chip exterior. The input circuits
4
receive the above-mentioned signals through the pads
2
. The signals received are amplified and output to the latching circuit
6
. Here, the address signals ADD
0
-ADD
5
are supplied so as to ensure a predetermined setup time or a predetermined hold time for a rising edge of the clock signal CLK. The latching circuit
6
has latches
6
a
corresponding to the address signals ADD
0
-ADD
5
, respectively. The latching circuit
6
accepts the address signals ADD
0
-ADD
5
in synchronization with a rising edge of the clock signal CLK and outputs the accepted signals to internal circuits.
Now, the operating frequencies of DRAMs have recently been on the increase and the above-mentioned setup time and hold time on the decrease. As a result, it has become necessary to lower the in-chip skew of the address signals ADD
0
-ADDS so that the address signals ADD
0
-ADD
5
are accepted with reliability. Specifically, as shown in
FIG. 1
, the wiring patterns of the address signals ADD
0
-ADD
5
extending from the input circuits
4
to the latching circuit
6
were formed to meander for equal lengths. Thus, the address signals ADD
0
-ADD
5
supplied from the pads
2
were transmitted to the latching circuit
6
almost at the same time.
In such a technique, however, the wiring patterns had to be formed in conformity to the longest. Actual DRAMs have a greater number of address signals than those shown in FIG.
1
. Besides, the pads for receiving these signals are often arranged in one direction on the chip, with a considerable distance between both end pads. This consequently elongated the wiring patterns for the address signals, giving rise to a problem that these wiring patterns increase in layout area to make the chip size greater. The increase in chip size directly contributes a rise in chip cost. Such a problem arises not only with the address signals but also with the wiring patterns for data signals.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit which surely accepts input signals in synchronization with a timing signal without any increase in layout area.
According to one of the aspects of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a plurality of receiving circuits each for receiving a plurality of input signals in synchronization with a timing signal. The input signals supplied to each of the receiving circuits are made equal in propagation delay times from their respective input terminals to the receiving circuit. Since the receiving circuits can receive the input signals of little skew, the timing margin required for the reception is minimized. That is, high speed operation becomes possible. At the same time, because the input signals corresponding to each individual receiving circuit are made equal in propagation delay time, the wiring for transmitting the input signals can be arranged in a minimum area. This can reduce the chip area, with reduction in chip costs.
According to another aspect of the semiconductor integrated circuit in the present invention, the propagation delay time is set by equalizing the lengths of wiring patterns through which the input signals are transmitted. Therefore, the propagation delay time of each input signal can be visually set with facility.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises decoders respectively corresponding to the receiving circuits. The decoders decode the input signals received by the receiving circuits. Since the input signals are made equal in propagation delay time by unit of decoding, each of the decoders can receive its input signals with no skew. As a result, it becomes possible to reduce the settling time of the decoder outputs.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a memory cell array having a plurality of memory cells. Each of the receiving circuits receives, as the input signals, a plurality of address signals for selecting the memory cells. This allows reduction in the settling time of the address decoder outputs.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises internal accepting circuits respectively corresponding to the receiving circuits. The internal accepting circuits accept the input signals received by the receiving circuits, in synchronization with internal timing signals generated in accordance with internal circuit operation. Since the input signals are made equal in propagation delay time by unit of acceptance by the internal accepting circuits, each of the internal accepting circuits can receive its input signals with no skew. This can increase the timing margins for the internal accepting circuits to accept their input signals under the internal timing signals.
According to another aspect of the semiconductor integrated circuit in the present invention, the receiving circuits are each formed corresponding to the destinations of wiring patterns. That is, the input signals can be supplied to internal circuits at an optimum timing in accordance with the layout of the internal circuits.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a memory cell array having a plurality of memory cells. Each of the receiving circuits receives, as the input signals, data to be written to the memory cells. Therefore, the data can be supplied at an optimum timing in accordance with the on-chip locations of the memory cells. This configuration is effective especially when a plurality of memory cell arrays (or memory cores) each having a plurality of memory cells are formed on a chip and the pieces of data corresponding to these memory cell arrays differ in bit number.
REFERENCES:
patent: 5473195 (1995-12-01), Koike
patent: 5724281 (1998-03-01), Nagaba
patent: 5986943 (1999-11-01), Isa
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Lebentritt Michael S.
Phung Anh
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