Input protection circuit and method of fabricating semiconductor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257356, 257357, 257360, 257361, 361 91, H01L 2362

Patent

active

056963971

ABSTRACT:
The present invention provides an input protection circuit including a first MOS FET including a source electrically connected to an input terminal and a drain and a gate both electrically connected to a grounding line, a second MOS FET including a source electrically connected to the input terminal and a drain and a gate, and a third MOS FET including a source electrically connected to a power line and a drain and a gate to both of which are electrically connected a drain and a gate of the second MOS FET. The input protection circuit shares a parasitic p-MOS transistor with an internal circuit, and hence it is no longer necessary to form a parasitic MOS transistor to be used only for an input protection circuit. Thus, the input protection circuit decreases the number of photomask using steps by one relative to a conventional protection circuit. In addition, the sharing a parasitic MOS transistor with an internal circuit makes it possible to prevent a current from running from an input terminal to a power line, even if a voltage higher than a source voltage is input to the input terminal. Thus, it is possible to enhance resistance to electrostatic breakdown, and fabricate an integrated circuit having high reliability with lower cost.

REFERENCES:
patent: 4609931 (1986-09-01), Koike
patent: 4949212 (1990-08-01), Lenz et al.
patent: 5272586 (1993-12-01), Yen
patent: 5532178 (1996-07-01), Liaw et al.

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