Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-27
2003-03-25
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S401000
Reexamination Certificate
active
06538291
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input protection circuit comprising MOS transistors for use in a semiconductor integrated circuit.
2. Description of the Related Art
In a semiconductor integrated circuit, input protection circuits are used for the purpose of preventing an electrostatic breakdown.
FIG. 1
is a circuit diagram showing an input protection circuit. This input protection circuit comprises a P-channel type MOS transistor
1
and an N-channel type transistor
2
connected in series. The source and gate of the P-channel type MOS transistor
1
are connected to a power supply terminal VDD in common. The source and gate of the N-channel type MOS transistor
2
are connected to a ground terminal GND in common. The serial connection point is connected to an input terminal, or an electrode pad
3
, and also connected to an internal circuit (not shown) through other wiring
4
.
FIG. 2
is a plan view showing the arrangement of source regions, a drain region, and electrodes in a MOS transistor which constitutes a conventional input protection circuit.
FIG. 3
is a sectional view taken along the line A—A of FIG.
2
. The reference numeral
5
represents a lightly-doped one conductivity type, or P
−
type semiconductor layer;
6
a heavily-doped opposite conductivity type, or N
+
type drain region;
7
N
+
type source regions;
8
a heavily-doped one conductivity type, or P
+
type backgate contact region;
9
gate electrodes;
10
an insulation film;
11
a drain electrode; and
12
a source electrode. In
FIG. 2
, the gate electrodes
9
, the drain electrode
11
, and the source electrode
12
are shown by double-dashed chain lines, and the insulation film
10
is omitted. The lower part of the MOS transistor is also omitted from FIG.
2
. The omitted part has the same configuration as that of the shown part, and hence the MOS transistor is generally symmetrical in the vertical direction.
Turning now to layout patterns, as shown in
FIG. 2
, the heavily-doped opposite conductivity type or N
+
type drain region
6
is arranged in a rectangular shape in the lightly-doped one conductivity type or P
−
type semiconductor layer
5
. The N
+
type source regions
7
are arranged in rectangular shapes beside both longer sides of the drain region
6
at a predetermined distance from the same. The gate electrodes
9
are arranged between the drain region
6
and the source regions
7
so as to extend along the longer sides of the drain region
6
. Moreover, the heavily-doped one conductivity type or P
+
type backgate contact region
8
is arranged at a predetermined distance from the drain region
6
. The backgate contact region
8
is shaped like a frame which is parallel to each side of the rectangular drain region
6
, so as to surround the drain region
6
, the gate electrodes
9
, and the source regions
7
.
As shown in
FIG. 3
, the insulation film
10
is formed over the P
−
type semiconductor layer
5
. The insulation film
10
is provided with contact windows which reach the drain region
6
, the source regions
7
, and the backgate contact region
8
. The drain electrode
11
is arranged in a rectangular shape so as to make electric contact with a plurality of points on the drain region
6
through contact windows in the insulation film
10
. The source electrode
12
is arranged in a frame shape so as to make electric contact with a plurality of points on the source regions
7
and backgate contact region
8
and with both longitudinal ends of the gate electrodes
9
through contact windows in the insulation film
10
.
The drain electrode
11
is connected to an electrode pad (not shown), and the source electrode
12
is connected to a ground terminal GND (not shown).
The input protection circuit of
FIG. 1
, when a high voltage resulting from static electricity is applied to the electrode pad
3
while the ground terminal GND is grounded and the power is not yet turned on, discharges the electrostatic charge to the ground terminal GND through the N-channel type MOS transistor
2
. As shown in
FIGS. 1 and 2
, if the static electricity applied to the electrode pad is of negative voltage, the PN junction between the drain region
6
and the semiconductor layer
5
is forward-biased for discharge. If the static electricity applied to the electrode pad is of positive voltage, the semiconductor layer
5
and the drain region
6
are reverse-biased for breakdown, and then enter a snapback state for discharge. Incidentally, the back gage contact region
8
has a guard-ring function of preventing electrostatic effects from extending to the outside of the guard ring, along with the function of electrically connecting the source electrode
12
to the semiconductor layer
5
.
As mentioned above, the negative-voltage static electricity applied to the electrode pad is discharged under the forward bias between the drain region
6
and the semiconductor layer
5
. The drain region
6
of rectangular shape, however, receives electric currents of higher densities flowing in from the backgate contact region
8
at the vicinities of both longitudinal ends than at the longitudinal center. This means easy current concentration in the vicinities of the longitudinal ends, facilitating breakdown there. In particular, when the electrode pad is connected to only one of the longitudinal ends of the rectangular drain electrode
11
, currents tend to concentrate on that end, producing a problem of especially easy breakdown on the electrode-pad-connected side. While this problem has been described in conjunction with a MOS transistor
100
to be used as the N-channel type MOS transistor
2
, the same problem occurs with MOS transistors having the same layout patterns as those of a MOS transistor
100
to be used as the P-channel type MOS transistor
1
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an input protection circuit in which the forward-bias current paths through a PN junction in a MOS transistor constituting the input protection circuit are partially made resistant to current flows so that local current concentration on the PN junction of the MOS transistor, resulting from the application of high voltage to the electrode pad is avoided to improve the breakdown voltage of the input protection circuit.
An input protection circuit according to the present invention comprises: a MOS transistor for discharging a high voltage applied to an electrode pad by means of a forward bias to a PN junction; and a resistance increasing element or device arranged on a part of a current path in the MOS transistor under the forward bias, whereby local current concentration on the PN junction is prevented.
In the present invention, the resistance increasing element or device is arranged on the current path through the MOS transistor's PN junction, in the vicinity of a point where local current concentration tends to occur when the MOS transistor discharges an electric charge induced upon the application of static electricity. This can avoid local current concentration under the forward bias to the PN junction, so that the MOS transistor included in the input protection circuit is prevented from damage.
The MOS transistor preferably includes: a lightly-doped one conductivity type semiconductor layer; a heavily-doped opposite conductivity type drain region having a rectangular pattern, formed in the semiconductor layer; and a heavily-doped one conductivity type backgate contact region formed in the semiconductor layer, patterned like a frame parallel to the rectangular pattern so as to surround the drain region. The resistance increasing element or device preferably include a lightly-doped opposite conductivity type diffusion layer formed between the drain region and the backgate contact region in the semiconductor layer, in the vicinity of a longitudinal end of the drain region at a predetermined distance from the drain region.
Here, the lightly-doped opposite type dif
McGinn & Gibb PLLC
Nadav Ori
NEC Corporation
Thomas Tom
LandOfFree
Input protection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Input protection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input protection circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3005564