Input protecting circuit in use with a MOS semiconductor device

Details Input protecting circuit in use with a MOS semiconductor device Input protecting circuit in use with a MOS semiconductor device

1988-12-28

1990-05-08

DeBoer, Todd E.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 58, 361 91, 361111, 357 2313, H02H 904

Patent

active

049243390

ABSTRACT:
A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.

REFERENCES:
patent: 3676742 (1972-07-01), Russell et al.
patent: 3819952 (1974-06-01), Enomoto et al.
patent: 4066918 (1978-01-01), Heuner et al.
patent: 4282556 (1981-08-01), Ipri
patent: 4692834 (1987-09-01), Iwahashi et al.
patent: 4760433 (1988-07-01), Young et al.
"NMOS Protection Circuitry", IEEE Transactions on Electron Devices, vol. ED-32, No. 5, May 1985, R. Rountree and Charles L. Hutchins.

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