Input/output transistors with optimized ESD protection

Details Input/output transistors with optimized ESD protection Input/output transistors with optimized ESD protection

1995-03-02

1996-02-20

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257344, 257408, H01L 2976

Patent

active

054931428

ABSTRACT:
An apparatus providing electrostatic discharge (ESD) protection in an input/output transistor. Disposed near the gate and the surface of the substrate is a lightly doped region. A sidewall oxide layer is selectively etched to extend laterally from a gate a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may laterally extend an appreciable amount in that direction. A heavily doped source and drain are implanted in the substrate at areas of the surface exposed by etching, the drain separated from the gate by the significant extent of sidewall oxide. Near the surface of the substrate, the drain is separated from the gate by a similar extent of the lightly doped region, which provides a resistance in series between the drain and gate for ESD protection. The source may also be separated from the gate by a lightly doped region of appreciable extent, which acts as a series resistance between the source and the gate to mitigate ESD. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.

REFERENCES:
patent: 4692781 (1987-09-01), Rountree et al.
patent: 4855620 (1989-08-01), Duvvury et al.
patent: 4933730 (1990-06-01), Shirato
patent: 5146298 (1992-09-01), Eklund
patent: 5278441 (1994-01-01), Kang et al.

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