Boots – shoes – and leggings
Patent
1991-12-06
1993-09-07
Shaw, Dale M.
Boots, shoes, and leggings
395800, 364DIG1, G06F 1516, G06F 1580
Patent
active
052436993
ABSTRACT:
A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.
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patent: 4623996 (1986-11-01), McMillen
patent: 4644346 (1987-02-01), Ito et al.
patent: 4862451 (1989-08-01), Closs et al.
patent: 4876644 (1989-10-01), Nuechterlein et al.
patent: 5008815 (1991-04-01), Hillis
patent: 5093827 (1992-03-01), Franklin et al.
Blank William T.
Kim Won S.
Nickolls John R.
Zapisek John
Barry Lance Leonard
MasPar Computer Corporation
Shaw Dale M.
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