Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2000-07-21
2004-04-20
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C711S002000, C710S003000
Reexamination Certificate
active
06725353
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89107992, filed Apr. 27, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an input/output register programming system and method. More particularly, the present invention relates to an input/output register programming system and method that use a set transmission value.
2. Description of Related Art
In most data input/output methods, data reading and writing is achieved through a corresponding input/output register. In fact, most inputs or outputs are carried out in a direct addressing mode. In other words, a fixed address is assigned to all input/output registers so that input/output operations are facilitated. However, when programming a group of input/output registers, the addresses of this group of input/output registers are not serially related to each other. When a non-contiguous register address is encountered during programming, a signal handshaking cycle must be executed. Hence, a lot of time is wasted in handling signal handshaking cycles when addresses of the registers are non-contiguous.
In executing multimedia function calls, since many programming parameters are needed, a large number of registers must be used. Because time needed to process these handshaking signals is correspondingly large, efficiency of multimedia function calls is likely to drop.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a first input/output register programming system that uses a set transmission value. The first input/output register programming system can be applied to any system that uses a write address and an input command for inputting data and a plurality of input/output registers. The first input/output register programming system includes an address decoder, a transmission setting register, a partitioning device, an internal address generator and a transmission space. The address decoder decodes write address to determine if the input command is an input/output register write command or a transmission setting register write command. According to whether the input command is an input/output register write command or a transmission setting register write command, an input/output register write enable signal or a transmission setting register write enable signal is issued. Input data written into the transmission setting register are to become set transmission values when the transmission setting register write enable signal is true. The set transmission value is used for representing the target region address of input command. When the transmission setting register write enable signal is false, the target region address represented by the set transmission value is output. Furthermore, the partitioning device divides the input data into a secondary address and stored data when the transmission setting register write enable signal is false. The internal address generator combines the secondary address and the target region address to produce an internal address. The input/output registers specified by the internal address inside the transmission space are used for storing the stored data.
The invention also provides a second input/output register programming system that uses set transmission values. The second input/output register programming system can be applied to any system that uses a write address and an input command for inputting data and a plurality of input/output registers. The second input/output register programming system includes an address decoder, a transmission setting register, a partitioning device, an internal address generator and a transmission space. The address decoder decodes write address to determine if the input command is an input/output register write command or a transmission setting register write command. Input data is written into the transmission setting register to become a set transmission value when the input command is the transmission setting register write command. The set transmission value is used to determine the target region address of the input command. The target region address represented by the set transmission value is output when the input command is an input/output register write command. Furthermore, the partitioning device divides the input data into a secondary address and stored data. The internal address generator combines the secondary address and the target region address to produce an internal address. The input/output registers specified by the internal address inside the transmission space are used for storing the stored data.
The invention also provides a third input/output register programming system that uses a set transmission value. The third input/output register programming system can be applied to any system that uses a write address and an input command for inputting data and a plurality of input/output registers. The input data includes a secondary address and stored data. The third input/output register programming system includes a transmission setting register, a partitioning device, an internal address generator and a transmission space. The transmission setting register stores a set transmission value for setting the target region address of an input command and is also capable of outputting the target region address. The partitioning device divides the input data into a secondary address and stored data. The internal address generator combines the secondary address and the target region address to produce an internal address. The input/output registers specified by the internal address inside the transmission space are used for storing the stored data.
This invention also provides an input/output register programming method that uses a set transmission value. First, a write address and an input command for inputting data are provided. The input data include a secondary address and stored data. By decoding the write address, whether the input command is an input/output register write command or a transmission setting register write command can be determined. The input data is stored as a set transmission value when the input command is a transmission setting register write command. The target region address represented by the set transmission value is output when the input command is an input/output register write command. The secondary address and the output target region address are combined to produce an internal address. Finally, the stored data are written into the internal address.
This invention also provides an input/output register programming method that uses a set transmission value. First, an input command for inputting data and a target region address is provided. The input data include a secondary address and stored data. By combining the secondary data and the target region address, an internal address is produced. Finally, the stored data are written into the internal address.
In brief, this invention uses a set transmission value and input command that includes a secondary address to produce an internal address. Through address exchange and the setting of transmission values, data in registers having non-contiguous addresses can be accessed as data in registers having contiguous addresses. Therefore, some handshaking cycles between registers are eliminated leading to a faster operating speed for the control system.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5500930 (1996-03-01), Fueki
patent: 6023750 (2000-02-01), Hansen et al.
patent: 6314506 (2001-11-01), Stanton et al.
J.C. Patents
Padmanabhan Mano
Song Jasmine
Via Technologies Inc.
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