Input/output processing system

Details Input/output processing system Input/output processing system

1999-12-06

2003-02-18

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S006130, C714S043000

Reexamination Certificate

active

06523138

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to input/output processing systems and more particularly, to an input/output processing system which connects a plurality of channels and a plurality of channel processors to allow each channel processor to control the channels.
As a computer system increases in scale, the number of input/output devices connected to the system has been increased in these years. In actual situations, however, the number of channels in the computer system cannot be increased satisfactorily due to physical and logical restrictions. As a result, for the purpose of improving the reliability of the computer system, in spite of the fact that it is desirable to connect the input/output devices to a plurality of channels, the conventional computer system can, in many cases, connect the input/output device to only one channel.
FIG. 14
is a block diagram of an arrangement of a prior art input/output processing system in a computer system. Explanation will be made as to the arrangement of the prior art input/output processing system. In
FIG. 14
, reference numeral
70
denotes an instruction processor (IP),
71
denotes a system controller (SC),
720
and
721
denote channel processors (CHP
0
, CHP
1
),
730
to
73
i
and
740
to
74
i
denote channels (CH
00
to CH
0
i
and CH
10
to CH
1
i
),
750
to
75
n
denote input/output devices (I/O
0
to I/On), and
76
denotes an input/output processor (IOP).
The prior art input/output processing system shown in
FIG. 14
includes the instruction processor (IP)
70
as a central processing unit, the system controller (SC)
71
connected to the instruction processor (IP)
70
, the two channel processors (CHP
0
and CHP
1
)
720
and
721
connected to the system controller (SC)
71
, the plurality of channels (CH
00
to CH
0
i
)
730
to
73
i
connected to the channel processor (CHP
0
)
720
, the plurality of channels CH
10
to CH
1
i
and
740
to
74
i
connected to the channel processor (CHP
1
)
721
, and the input/output devices (I/O
0
to I/On)
750
to
75
n
connected to the respective channels (CH). In the illustrated example, only one (I/Om)
75
m
of the plurality of input/output devices is connected to the two channels (CH
0
i
and CH
10
under control of the different channel processors (CH
0
i
and CH
10
) and the other input/output devices are connected to respective one of the channels.
In the input/output processing system having such an arrangement as mentioned above, if the channel processor (CHP
0
)
720
became faulty for example, then the channels (CH
00
to CH
0
i
)
730
to
73
i
cannot be used. As a result, the input/output devices (I/O
0
to I/O(m−1)) 750 to 75(m−1) cannot be used because these input/output device have exchange paths. In the illustrated example, however, since the input/output device (I/Om)
75
m
has an exchange path for the channel (CH
10
)
740
connected to the normal channel processor (CHP
1
)
721
, the input/output device can be continuously used.
As has been explained above, the prior art input/output processing system is arranged so that the plurality of channels are controllably connected to each one of the channel processors. For this reason, the aforementioned prior art input/output processing system has had a problem that, if one of the channel processors connected to the many channels leading to the many input/output devices for controlling the channels becomes faulty, all the input/output devices connected to the faulty channel processor cannot be used because of no exchange paths therefor, resulting in that the damage of the system becomes severe.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an input/output processing system which can solve the above problem in the prior art, and wherein channel processors are multiplexed so that a plurality of channels are connected to a plurality of channel processors to allow the plurality of channel processors to control the respective channels, whereby, even when one of the channel processors became faulty, the channels under control of the faulty channel processor can be controlled by the other normal channel processor and thus can be continuously used.
In accordance with an aspect of the present invention, to achieve above object, there is provided an input/output processing system which comprises a central processing unit, a plurality of channels performing data transfer with input/output devices, and a plurality of channel processors for controlling the plurality of channels, wherein each of the plurality of channels has paths connected to the plurality of channel processors and has first means, when it is desired for the central processing unit to initiate one of the channels, for determining one of the channel processors which initiates the channels in question, and the first means is a table showing relationships among logical channel numbers to be used by a program, physical channel numbers to be used by hardware, and usable channel processor numbers.
Another aspect of the invention provides second means, when an interruption is applied from the input/output device in question to the central processing unit, for determining one of the channel processors interruptable from the channel connected to the associated input/output device, wherein the first means is provided in a main storage, and the second means is provided in each of the channels.
In accordance with a further aspect of the invention, the first and second means are changed when one of the plurality of channel processors have become faulty in such a manner that the other normal channel processor initiates all the channels and receives an interruption from all the channels to perform input/output operation.
In accordance with another aspect of the invention, a fault in the channel processor is detected by a service processor, an instruction is issued from the service processor to the other channel processor to connect the channels so far connected to the faulty channel processor to the other normal channel processor, and the first and second means are changed by the channel processor receiving the instruction; or after the faulty channel processor has been replaced by the normal channel processor during operation of the system, by initializing the replaced new channel processor by the service processor, an instruction is issued from the service processor to the new channel processor to connect the channels so far connected to the faulty channel processor to the new channel processor, and changing the first and second means by the new channel processor receiving the instruction.


REFERENCES:
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patent: 4974147 (1990-11-01), Hanrahan et al.
patent: 5297262 (1994-03-01), Cox et al.
patent: 5438675 (1995-08-01), Fujioka
patent: 5502728 (1996-03-01), Smith, III
patent: 5504882 (1996-04-01), Chai et al.
patent: 5668943 (1997-09-01), Attanasio et al.
patent: 6216179 (2001-04-01), Murata et al.

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