Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-26
2004-03-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06701491
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for verifying and inspecting a designed digital circuit, and more particularly to an input/output probing apparatus which is capable of implementing a designed digital circuit as a programmable chip or as an order-built type semiconductor chip actually by hardware and capable of quickly verifying and inspecting it on an emulation basis, and a method using the same. Further, the present invention relates to a mixed emulation/simulation method which is capable of implementing a designed digital circuit as a programmable chip or as an ASIC semiconductor chip actually by hardware, capable of automatically switching from emulation to simulation executed by means of a simulator on a computer during emulating process, or reversely, capable of automatically switching from simulation executed on the computer by the simulator to emulation, thereby performing emulation and simulation in turn more than one time for verification and a mixed emulation/simulation verifying apparatus therefor.
2. Description of the Related Art
Recently, as a design for an integrated circuit and a semiconductor process technique are being rapidly developed, a design of a digital circuit tends to be enlarged and its construction becomes complicate. Accordingly, as competition in the market turns keen more and more, a method for verifying a designed circuit quickly and effectively is sought to meet the necessity.
Up to now, generally, a simulator, an approach based on software, has been employed to verify a designed digital circuit. Thanks to its advantage of using various delay models for a circuit, the simulation-based verifying method using the simulator allows a timing verification as well as a functional verification, and above all, it provides a perfect visibility for every signal line existing in a circuit during debugging.
However, as for the simulator, since a software code consisting of sequential instruction sequences, which is obtained by modeling the design verification circuit by software, is to be sequentially performed on computer, time for verification is taken for a long time, with a limitation that it fails to be integrated with a peripheral hardware environment for In-Circuit Emulation (referred to as an ICE, hereinafter).
Moreover, referring to the verification through simulation, since performance of a computer dependent on a simulation software and a single processor fails to come up with the complexity of a digital circuit of tens of thousands of gates which are rapidly increased, recently, it incurs an extremely long time to perform a simulation for a general design verification.
Comparatively, a hardware emulation based design verification method, that actually implements a designed circuit as a chip to use it, is advantageous in that since the digital circuit is verified while being parallely operated, design verification can be possibly carried out at a million time speed at the maximum compared to that of the simulation, and ICE environment is possibly constructed with respect to a peripheral hardware environment for integrated verification.
However, the emulation is not good for debugging compared to the simulation. The reason for this is that the visibility showing logic values of numerous signal lines existing in the circuit implemented with programmable chips or ASIC chips is exorbitantly degraded compared to simulation.
As a core device for emulation-based design verification, reusable field programmable devices (referred to as ‘RFPD’, hereinafter), that is, programmable chips, are employed. The RFPD includes a field programmable gate array and a complex programmable logic device. These days, with development of a semiconductor technique, the RFPD is highly integrated, making it possible to use a single RFPD or a very few RFPD for complex digital circuits and prototype it.
Unlike the implementation of a circuit using the ASIC chip, in case that a circuit is implemented by using the RFPD, it is advantageous in that it can be carried out in the field at a low cost, and time and expense are considerably reduced to correct a bug as being found.
The feature of the present invention also can be applied to a case of using an ASIC chip using a technique such as a standard cell or to a gate array in the same manner as well as the case of using the RFPD for implementation of the design verification circuit, but in the description of the present invention, using of the RFPD is taken for explanation's convenience.
As mentioned above, though prototyping can be economically performed owing to the development in the highly integrated semiconductor technique, since the numerous signal lines on the digital circuit, the target for design verification in prototyping, mostly exist inside the RFPD, it is difficult to probe the signal lines, degrading visibility for debugging. This problem would be more serious in the future when more highly integrated RFPD is expected to be used.
In order to solve the problem, a method is required for performing an effective and rapid probing even in the case that the signal lines of the circuit exist inside the chip, so that a circuit subjected to design verification as being implemented in the RFPD can be effectively and rapidly debugged.
Besides, in order to maximize the efficiency for design verification of a digital circuit, a method of mixedly using emulation and simulation appropriately in turn during design verifying process is required.
That is, a high speed function verification is carried out to the point of time when and in a specific situation where a very fine identification is required on the emulation basis for design verification. Thereafter, the verifying method is automatically switched from an emulation basis to a simulation basis to perform a functional verification or a timing verification with a 100%-perfect visibility for the target circuit of verification.
In this respect, switching between emulation and simulation is repeated more than one time, as necessary, to thereby maximize efficiency of the verification.
However, to date, in case that a hardware board (referred to as ‘arbitrary prototyping board’, hereinafter) on which a digital circuit is implemented with the RFPD, the programmable chip, or with a general ASIC semiconductor chip, is subjected to a design verification on the emulation basis, no input/output probing apparatus using an open architecture that can perform debugging rapidly and effectively even for a hardware board, not limiting to a specific hardware board, and no input/output probing method has been presented.
And, a general tendency shows that designers design a digital circuit by using a gated clock or a locally generated clock, rather than designing a fully synchronous circuit, to reduce a power consumption or due to various reasons.
However, such asynchronous factors make input/output probing for a circuit, especially, an input probing, very difficult. In addition, no input/output probing method has been proposed to cope with such a general situation.
Moreover, there has not been proposed any method and apparatus for mixedly using emulation and simulation for verification to thereby remove the shortcomings of the emulation-based verification method, in a manner of employing the hardware board on which an arbitrary ASIC semiconductor is mounted that implements a circuit subjected to a design verification including the asynchronous factors and an arbitrary simulator.
Especially, in case where simulation is first performed and emulation is subsequently performed, before emulation starts, memory devices and memories which exist in a circuit implemented in the RFPD that performs emulation are to have the same logic values as the logic values at the current time point of the memory devices (flipflops or latches) and the memories (RAM or ROM) of a design verification target circuit obtained by simulation.
However, in preparation for an asychronous situation in which a gated clock and a locally generated clock signal are
Levin Naum
Senniger Powers Leavitt & Roedel
Siek Vuthe
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