Input/output line structure of a semiconductor memory device

Details Input/output line structure of a semiconductor memory device Input/output line structure of a semiconductor memory device

2001-01-10

2002-02-05

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S051000

Reexamination Certificate

active

06345011

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-00940, filed on Jan. 10, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to an arrangement of input/output lines and a circuit associated with sense amplifiers in a semiconductor memory device.
BACKGROUND OF THE INVENTION
A general arrangement of a semiconductor memory device, as shown in
FIG. 1
, includes a divided array of memory banks and a peripheral circuit. Assuming that the semiconductor memory device formed on semiconductor chip
1
has a storage capacity of 128 Mb, four banks BANK
1
~BANK
4
each has a capacity of 32 Mb. The peripheral circuit disposed between the memory banks at the vertical center of the chip
1
includes circuits for decoding, buffering, and data input/output.
In constructing a 32 MB memory bank, as shown in
FIG. 2
, a row decoder
20
and column decoder
30
are positioned on the sides of the memory bank. 8K (K is 210) wordlines (IWL) and 4K bitline (BL) pairs are arranged in a matrix form. The memory array of 32 Mb in the memory bank is divided into sixteen memory blocks
40
(designated also MB
0
~MB
15
) along a row direction. Each of these memory blocks has a storage capacity of 2 Mb with 512 wordlines and 4K bitlines. 1K (1024) column selection lines CSL
0
~CSL
1023
extending from the column decoder
30
are arranged on and over the memory array, with each column selection line corresponding to four bitlines.
For a given cycle, two wordlines for each memory bank are activated. For example, the row decoder
20
selects one memory block (e.g., MB
1
) among the memory blocks MB
0
~MB
7
and one memory block (e.g., MB
9
) among the memory blocks MB
8
~MB
15
, and then selects one wordline in each of the selected memory blocks MB
1
and MB
9
. Namely, two wordlines (WL) are selected when one memory bank is selected, and other memory blocks in the selected memory bank are non-selected.
FIG. 3
shows the section A in dashed outline of
FIG. 2
, including the upper half of memory block MB
1
and surrounding circuitry. Between adjacent memory blocks, a sense amplifier block is positioned. For instance, sense amplifier blocks SABLK
0
and SABLK
1
are interposed between the memory blocks MB
0
and MB
1
, and between the memory blocks MB
1
and MB
2
, respectively. The sense amplifier block comprises bitline isolation regions
50
and
60
, bitline precharging/equalizing region
70
, P-channel sense amplifier region
80
, N-channel sense amplifier region
90
, and input/output gating region
100
(in dashed outline). See U.S. Pat. No. 5,761,123 entitled SENSE AMPLIFIER CIRCUIT OF A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, relevant to circuit elements provided to the bitline isolation regions, the precharging/equalizing region, and the sense amplifier regions.
In the input/output gating region
100
, four complementary pairs of input/output lines, IOi, /IOi, IOj, /IOj, IOk, /IOk, IOl, and /IOl, are arranged perpendicular to the bitlines, and column selection gates GT are connected between bitline pairs and input/output line pairs. When a row of the memory block MB
1
is selected by the row decoder
20
and a column selection line (e.g., CSL
0
) is selected by the column decoder
30
, bitline pair BL
0
and /BL
0
is connected to the input/output line pair IOi and /IOi located on the left side of MB
1
, through the corresponding column selection gate pair whose gates are coupled to CSL
0
. Also, BL
2
and /BL
2
are connected to IOj and /IOj arranged at the left side of MB
1
, through their corresponding column selection gates whose gates are also coupled to CSL
0
.
At the same time, BL
1
and /BL
1
are connected to IOi and /IOi arranged at the right side of MB
1
, and BL
3
and /BL
3
are connected to IOj and /IOj arranged at the right side of MB
1
, through their corresponding column selection gates whose gates are coupled to CSL
0
. Thus, one of the column selection lines can connect four bitline pairs to four input/output line pairs alternately arranged on the either side of the memory block MB
1
. Since two wordlines (WL signals corresponding to MB
1
, MB
9
) are activated upon the selection of one memory bank, data of four bits for each wordline are transferred to four corresponding input/output line pairs. As a result, eight bits are normally read out from one selected memory bank, in keeping with an 8-bit data structure.
If two column selection lines (e.g., CSL
0
and CSL
512
) are selected at the same time, 8-bit data are read out from the selected memory block MB
1
by the sense amplifier block corresponding thereto. In more detail, when CSL
0
is selected, four bitline pairs BL
0
, /BL
0
, BL
1
, /BL
1
, BL
2
, /BL
2
, BL
3
, and /BL
3
are connected to their corresponding input/output lines IOi, /IOi, IOj, and /IOj. In the same manner, the bitline pairs of BL
2048
and /BL
2048
, and of BL
2050
and /BL
2050
, are connected to the input/output line pairs of IOk and /IOk, and of IOl and /IOl, respectively, the input/output line pairs being arranged at the left side of MB
1
, through their corresponding column selection gate GT whose gates are coupled to CSL
512
. And the bitline pairs of BL
2049
and /BL
2049
, and of BL
2051
and /BL
2051
, are connected to the input/output line pairs of IOk and /IOk, and of IOl and /IOl, respectively, the input/output line pairs being arranged at the right side of MB
1
, through their corresponding column selection gate GT whose gates are coupled to CSL
512
.
Therefore, it can be seen from
FIG. 3
that eight bitline pairs are each connected to eight input/output line pairs alternately arranged on either side of the selected memory block MB
1
when two column selection lines (e.g., CSL
0
and CSL
512
) are activated at the same time. Since two wordlines are selected in a given memory bank, activation of two column selection signals enables 16-bit data to be read out of the selected memory banks.
It is possible to alternate between the 8-bit and 16-bit data read-out pattern in the array architecture shown in FIG.
3
. It is also possible to construct a 4-bit data structure by multiplexing the input/output line pairs with additional column address bits. Other bitlines and selection gates involved in the activation of other column selection lines are operationally arranged in the same configuration as described above.
FIG. 4
shows a layout pattern of the circuit arrangement of
FIG. 3
, wherein plural gate lines
102
made of polysilicon layers are formed over plural N+ active regions
101
. The plural bitlines and the plural active regions
101
are connected at plural contact regions
11
, and the active regions and input/output lines made of a metal or conductive material are connected at plural contact regions
13
.
The width of the input/output gating region, L, is determined by an integration density dependent upon the number of input/output lines disposed therein. In the gating region interposed between the adjacent memory blocks, eight input/output lines are arranged to provide an efficient data access operation, alternately positioned on either side of a memory block. However, a chip size of a memory device becomes even smaller as the size of electronic apparatus employing the memory device becomes smaller. The density of a memory device, which must is increase, is greatly influenced by repetitive patterns of the signal lines such as bitlines and input/output lines. As may be seen from
FIG. 4
, the regular horizontal arrangement of the eight input/output lines within a given sense amplifier block leaves inoperable regions thereof having no contacts to the active regions. This causes the width L to be unnecessarily and undesirably extended. Accordingly, there is a need for a more efficient input/output line arrangement.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an efficient input/output line arrangement that is advantageous in re

Affiliated with

Also associated with

Rating

Input/output line structure of a semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input/output line structure of a semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input/output line structure of a semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2962191