Input/output line sharing apparatus of semiconductor memory...

Details Input/output line sharing apparatus of semiconductor memory... Input/output line sharing apparatus of semiconductor memory...

2007-06-12

2007-06-12

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S189020

Reexamination Certificate

active

11321518

ABSTRACT:
Provided is an input/output line sharing apparatus of a semiconductor memory device. In this apparatus, a global input/output line is shared by a data line signal and a test mode signal, and an input/output line between test mode signals is shared. The apparatus comprises a global input/output line, a first control signal generating unit configured to generate a test mode control signal from a test mode register set signal, a multiplexer configured to output a signal selected from a data line signal and a test mode signal to the global input/output line in response to the test mode control signal, and a latch unit configured to store the test mode signal outputted from the global input/output line in response to the test mode control signal.

REFERENCES:
patent: 5404055 (1995-04-01), Shankar et al.
patent: 6061290 (2000-05-01), Shirley
patent: 6294925 (2001-09-01), Chan et al.
patent: 6498755 (2002-12-01), Takahashi et al.

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