Input/output device managed timer process

Details Input/output device managed timer process Input/output device managed timer process

1999-09-17

2003-07-15

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S044000

Reexamination Certificate

active

06594787

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an input/output (I/O) device managed timeout process.
BACKGROUND OF THE INVENTION
Computers are becoming ever more powerful, faster, and versatile. Correspondingly, the software being developed to harness the power of the newer computers are becoming more complex and sophisticated. With the advent of the Internet and vast improvements in the networking, telecommunications, and database fields, computer software is becoming even larger and more complex. For instance, an operating system can multi-task several different software applications, each of which can have multiple tasks, processes, and threads all running at the same time. Furthermore, devices such as modems, network interface cards, scanners, printers, graphics subsystems, audio cards, digital cameras, hard disks, CD ROM drives, etc., greatly add to the software complexity of monitoring, instructing, and otherwise communicating with these additional devices.
The potential downside to these enhanced capabilities and devices is that software glitches may periodically occur. Even a relatively minor software error can crash the entire system, resulting in lengthy, aggravating, and costly downtimes. In worst case scenarios, software glitches might cause critical data to be lost or corrupted.
In an effort to improve the reliability of software, developers have commonly relied upon the use of timers. Typically, a timer is used to monitor certain events to ensure that they function properly. A timeout condition is set to expire after a certain amount of time has elapsed. For example, suppose that a certain task is initiated and it is expected to be completed after a certain period of time. A timer can be set to elapse after that period of time. If the task is successfully completed within the allotted time, the timeout is canceled. Otherwise, if there happens to be a malfunction, the elapsed time expires and a timeout condition is generated. Thereupon, the system now knows that an error has occurred.
At this point, there are several options: an error condition can be generated and reported to a human operator who may then take appropriate corrective action; a separate piece of software may be notified of the error and initiated to correct the error condition; or the original piece of software may be re-executed with the hope that it will properly function the second time around. Hence, rather than trusting that a job, process, activity, communication, or some other operation will finish successfully, a timer can be used to bound the operation at issue. This facilitates a smoother running system and improves overall system reliability.
For larger computer systems, timers can be implemented in hardware. A separate processor can be dedicated to handling timers and timeout conditions. However, larger computer systems are more expensive to design and manufacture. Consequently, timers are most often implemented in software—specifically, as part of the kernel facility of the computer's operating system (O/S), such as UNIX, Windows, NT, Linux, etc.
Unfortunately, timers have a fair degree of associated overhead. First, the timer has to be initiated. Next, the timer has to be monitored while it is running. If the task successfully completes, the timer has to be canceled. Otherwise, the operating system has to detect and respond to any potential timeouts.
The incremental cost of implementing a single timer is slight compared to the benefit attained. However, a single O/S can have many, multiple tasks running at any given time. This is especially the case with client/server, Internet/Web, and network/communications applications. The large number of activities, each of which may be covered by one or more timers, can dramatically impact and eventually overwhelm the computer's processing capability. Thus, computer system designers are faced with a dilemma: either pare back the number of timers and suffer the risk of potentially unstable software, or improve the overall reliability of the system by implementing more timers at the expense of degraded performance.
Accordingly, what is needed is a system or method for implementing timers such that timer overhead to the O/S is minimized, so that the robustness of a computer system is enhanced by implementing timers while the impact associated with operating these timers is substantially minimized. The present invention provides a novel solution to the above needs.
These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
SUMMARY OF THE INVENTION
The present invention provides a novel solution for using timers in such a way that they can be implemented with minimal overhead to the O/S. With the present invention, the robustness of a computer system is enhanced by implementing timers while the impact associated with operating these timers is substantially minimized.
The present invention pertains to a system and method thereof managed by an input/output device for monitoring elapsed time for a transaction. In the present embodiment, a computer system executes an application to initiate a transaction. The input/output device is communicatively coupled to the computer system and receives the transaction from the computer system. The input/output device is adapted to have a timer for measuring time until, for example, a response to the transaction is generated. The input/output device cancels the timer provided a cancellation condition is satisfied and otherwise identifies a timeout condition.
In the present embodiment, the input/output device can have a plurality of timers that each monitor one of a plurality of multiple concurrent transactions.
In the present embodiment, the input/output device generates a signal to indicate the timeout condition. In one embodiment, the signal is sent from the input/output device to the computer system's operating system. In another embodiment, the transaction is sent from the application to the input/output system bypassing the computer system's operating system, and the signal from the input/output device is sent to the application also bypassing the operating system.
In one embodiment, the cancellation condition is a time period allotted for the response to the transaction. The input/output device cancels the timer provided the response to the transaction occurs within the time period allotted and identifies a timeout condition when the time period allotted is exceeded.
In one embodiment, the time period allotted for the response is specified in a control command associated with the transaction received by the input/output device from the computer system.
In one embodiment, an expected response to the transaction is specified. The input/output device uses the expected response to recognize the response to the transaction.
In one embodiment, the input/output device is a peripheral device (e.g., a graphics adapter, video adapter, etc.) that executes the transaction in response to the application. In another embodiment, the input/output device is a communication device (e.g., a network interface card, network adapter, etc.) that couples the computer system to an external device that executes the transaction in response to the application.


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patent: 6012090 (2000-01-01), Chung et al.
patent: 6173339 (2001-01-01), Yorimitsu

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