Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1998-10-22
2001-06-26
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S005000, C710S020000, C710S039000, C710S040000, C710S044000
Reexamination Certificate
active
06253260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and system for queuing data access requests (DAR) according to a priority system.
2. Description of the Related Art
In current storage systems, a storage controller manages data transfer operations between a direct access storage device (DASD), which may be a string of hard disk drives or other non-volatile storage device(s), and host systems and their application programs. To execute a read operation presented from a host system, i.e., a data access request (DAR), the storage controller must physically access the data stored in tracks in the DASD. A DAR is a set of contiguous data sets, such as tracks, records, fixed blocks, or any other grouping of data. The process of physically rotating the disk in the DASD to the requested track then physically moving the reading unit to the disk section to read data is often a time consuming process. For this reason, current systems stage data into a cache memory of the storage controller in advance of the host requests for such data.
A storage controller typically includes a large buffer managed as a cache to buffer data accessed from the attached DASD. In this way, data access requests (DARs) can be serviced at electronic speeds directly from the cache thereby avoiding the electromechanical delays associated with reading the data from the DASD. Prior to receiving the actual DAR, the storage controller receives information on a sequence of tracks in the DASD involved in the upcoming read operation or that data is being accessed sequentially. The storage controller will then proceed to stage the sequential tracks into the cache. The storage controller would then process DARs by accessing the staged data in the cache. In this way, the storage controller can return cached data to a read request at the data transfer speed in the storage controller channels as opposed to non-cached data which is transferred at the speed of the DASD device.
A “hit” is a DAR that can be serviced from cache, whereas a “miss” occurs when the requested data is not in cache and must be retrieved from DASD. With the International Business Machines Corporation (IBM) 3990 Storage Controller, if a miss occurs, the storage controller disconnects from the channel and then accesses the DASD to retrieve the requested data. After retrieving the requested data from the DASD and storing the data in cache, the storage controller then reconnects to the channel and the requesting device, e.g., host, and returns the retrieved requested data. If there are multiple channel paths between a host and I/O device, then the storage controller can reconnect on any of the multiple channel paths to return the requested data to the I/O device. If retrieved data for multiple DARs are queued against a channel, then the storage controller typically uses a First-in-First-Out (FIFO) algorithm to determine which retrieved data request to return to the channel. Moreover, if there are multiple cache misses and multiple DARs are queued against a single I/O device or logical volume, then the storage controller typically uses a FIFO algorithm to execute queued DARs against the I/O device or logical volume. The servicing of DARs by a storage controller is described in IBM publication “Storage Subsystem Library: IBM 3990 Storage Control Reference (Models 1, 2, and 3)”, IBM document no. GA32-0099-06, (IBM Copyright 1988, 1994), which publication is incorporated herein by reference in its entirety.
There is a need in the art for an improved method for processing DARs and returning DARs to a channel.
SUMMARY OF THE PREFERRED EMBODIMENTS
To provide improvements over the prior art, preferred embodiments disclose a system and method for processing a data access request (DAR). A processing unit receives a DAR, indicating data to return on a channel, and priority information for the received DAR. The processing unit retrieves the requested data for the received DAR from a memory area and determines whether there is a queue of data entries indicating retrieved data for DARs to transfer on the channel. The queued DAR data entries include priority information. The processing unit processes at least one data entry in the queue, the priority information for the data entry, and the priority information for the received DAR to determine a position in the queue for the received DAR. The processing unit then indicates that the received DAR is at the determined position in the queue and processes the queue to select retrieved data to transfer on the channel.
In further embodiments, the processing unit receives a DAR indicating a data request to return on a channel and information indicating a priority of the received DAR. The processing unit then determines an address in the memory area of the data to retrieve for the received DAR and processes a queue indicating multiple DARs queued against the address. Priority information is associated with the queued DARs. The processing unit processes at least one DAR entry indicated in the queue, the priority information for the DAR entry, and the priority information for the received DAR to determine a position in the queue for the received DAR. The processing unit then indicates that the received DAR is at the determined position in the queue, processes the queue to select a DAR, and accesses the second memory area to retrieve the requested data for the selected DAR.
Prior art systems return retrieved data to a channel and execute I/O requests according to FIFO and other methods that do not take into account the priority of the DARs. Preferred embodiments assign a priority to a DAR and then process the priority information when determining which DAR to return on a channel or execute against an address. Thus, preferred embodiments provide a system for processing DARs according to an assigned priority of the DAR. Further embodiments increment lower priority queued DARs when a higher priority DAR is added to the queue. This insures that lower priority DARs are not continually ignored as new entries are added to the queue.
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Beardsley Brent Cameron
Iskiyan James Lincoln
Yudenfriend Harry Morris
Cao Chun
International Business Machines - Corporation
Konrad Raynes & Victor
Lee Thomas
Victor David W.
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