Input/output circuitry for programmable logic devices

Details Input/output circuitry for programmable logic devices Input/output circuitry for programmable logic devices

2000-03-24

2001-05-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06225823

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices, and more particularly to circuitry for use in the input and/or output portions of programmable logic devices.
Illustrative programmable logic devices are shown in Cliff et al. U.S. Pat. No. 5,689,195, Huang et al. U.S. Pat. No. 5,764,080, Reddy et al. U.S. Pat. No. 5,977,793, and McClintock et al. U.S. Pat. No. 5,999,016, all of which are hereby incorporated by reference herein in their entireties.
As programmable logic devices become larger and therefore have more input/output (“I/O”) pins, the complexity and flexibility with which the user may want to control the various pins tends to increase. The “control” thus referred to includes such functions as output enable, clock, clock enable, clear, etc. because very large programmable logic devices have the capability of performing so many different functions, parallel control of all the I/O pins on the device may not always be compatible with the uses to which the core logic of the device can be put. On the other hand, full individual control of all aspects of the operations of all I/O pins on the device is probably wasteful of device resources, especially since many uses of the device will probably want parallel control of at least some functions of some I/O pins.
In view of the foregoing, it is an object of this invention to provide improved circuitry for controlling I/O pins on programmable logic devices.
It is a more particular object of this invention to provide I/O control circuitry for programmable logic devices which effects a good mix of both parallel and individual control of I/O pin functions and operation.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic devices with I/O control signal buses that extend to large numbers of the I/O pins on the device but that are programmably segmentable into a plurality of segments, each of which extends to only an associated subset of the I/O pins. Each segment of an I/O control signal bus can be driven separately (e.g., by programmable logic on the device or by a special input pin). Thus each segment can provide a separate control signal to the I/O pins that it serves. Alternatively, two or more segments of a bus can be programmably connected to one another. Then the drive for only one of the connected segments is used and all the connected segments carry the same signal to all of the I/O pins served by those segments.
In addition to the foregoing, each I/O pin preferably includes circuitry for allowing individual selection of control signals from several sources, such as several adjacent I/O control signal buses of the type described above or logic circuitry near the I/O pin on the device.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.


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