Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-10-15
2003-09-23
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S037000, C326S038000, C326S082000
Reexamination Certificate
active
06624656
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, such as configurable system logic devices and configurable system-on-chip products. More specifically, the present invention relates to a method and structure to provide an input/output circuit with user programmable functions.
DISCUSSION OF RELATED ART
The input/output (I/O) circuit of a conventional integrated circuit (IC) acts as an interface between the integrated circuit and the outside world. Conventional ICs have pre-determined internal wired connections. In general, the signals passed through the I/O circuit of a conventional non-programmable IC are pre-defined and come from hardwired locations. As a result, the I/O pins of the IC have known state requirements. For example, a particular I/O pin may need to be grounded when it is not receiving a signal from an external source.
Typical circuitry within a conventional I/O circuit includes buffers (input and output) and registers (for input, output, and output enable signals). I/O circuit design attempts to optimize switching speed while minimizing switching noise. The switching speed of a signal, typically a clock signal, is the time it takes to transition from one logic state to another. The amount of switching noise produced is in part attributable to the amount of overshoot occurring in the transition of the clock signal from one logic state to another. I/O circuit register design attempts to optimize setup and hold times of the register relative to a known clock signal. The setup time of a register is the amount of time prior to a controlling clock edge during which a data signal must not change. The hold time of a register is the amount of time after a controlling clock edge during which a data signal must not change. If a data signal changes during the setup time or hold time, the signal at the output of the register is unpredictable.
A short setup time and a zero or negative hold time relative to a clock signal are very desirable. However, as the hold time relative to a clock signal becomes more negative, the setup time relative to the same clock signal becomes larger. Therefore, to conventionally optimize hold times, the delay on the data input of a register relative to a clock signal is carefully simulated to make the hold time as near zero as possible.
Programmable logic, such as Field Programmable Logic devices (FPLD) and Configurable System Logic (CSL) resident on Configurable Systems on a Chip (CSoC), provide built-in circuits that can be programmably interconnected, thus allowing a user to implement different designs “in the field” using the device. Typically, these designs are implemented by using Computer-Aided Design (CAD) “Place and Route” software. The CAD Place and Route software determines the placement of the designed circuits on the CSL and programs the memory elements that control the interconnections of the designed circuits.
Additional requirements beyond those of conventional non-programmable integrated circuits are needed due to the programmable nature of the CSL. For example, the arrangements of designed circuits on the CSL must facilitate implementation of useful functions by CAD software. This facilitation is typically accomplished by providing a wide selection of functional blocks and routing resources and providing a programmable means to connect both blocks and routing. Unfortunately, more flexible programmability of the CSL causes more complex CSL production testing procedures.
In production testing, the CSL must be programmed a large number of times in differing configurations to exhaust the combinations of possible interconnections of built-in circuits. As the flexibility of programming the CSL increases, the number of possible combinations of interconnections of built-in circuits increases. The cost of production of the CSL increases with the increase in complexity of CSL testing procedures.
During programming of the configuration memory elements, the internal logic of the CSL is unstable and unpredictable. The internal signals from this logic may be provided to output buffers and be driven to off-chip components. Therefore, a CSL requires a means to generate predictable states in the programmable I/O circuitry (PIO) of the CSL. The PIO performs the I/O function of the CSL.
Conventionally, using a tri-state buffer in an IOB while connecting the output pad of the IOB to a “weak pull-up” circuit is adequate in most situations. A weak pull-up circuit connected to an output pad provides a connection to a logic one that can be easily overcome by a signal asserted on the output pad. For example, Xilinx Inc. provides a weak pull-up circuit and a tri-state buffer in their IOB shown on page 4-25 of the Xilinx Programmable Logic Data Book, Version 1.03 (Jul. 30, 1996). A conventional pull-up circuit as described above limits the flexibility of a system designer by limiting the options available for defining a given logic state on the output pad.
Some IOBs within conventional FPGAs allow input signals to pass directly into selected routing channels. However, the number of channels available for a direct connection to a input terminal providing input signals is seriously limited. Other IOBs have latched or registered input signals before routing the signals into other routing channels. However, this latching or registering significantly increases the circuit area as well as the delay involved in selecting signals for routing.
Conventional programmable logic architectures comprising homogeneous arrays of smaller tiles commonly utilize a unique design and layout at each edge of the tile array to control the I/O interfaces between the logic array and external signals. Although the function and connectivity of the tile at each edge may be individually customized to take particular advantage of the location of the tile, the expense of this customization is greatly increased effort for design, verification, and layout.
Therefore, a need arises for an improved IOB which increases the number of channels available for direct connection to an input terminal while reducing circuit area and routing delay. Further, a need arises for an I/O block tile that makes externals driven or received by the tile similarly available to internal tiles without regard to the edge location of the tile.
SUMMARY OF THE INVENTION
The I/O circuit of the present invention provides optimal flexibility and performance using a number of different structures and methods.
The present invention provides a combination control circuit for an input pad wherein the signal on the pad may be pulled up to a logic one, pulled down to a logic low, or pulled to the logic value present on the input pad.
The present invention uses a configuration signal to select a value for an enable signal to either disable an output buffer during configuration, or to enable the output buffer according to a programmed value of a memory element. If the output buffer is enabled during configuration, the driven value can be programmed by memory elements. If the output buffer is disabled during configuration, the output pad can be pulled up to a logic one or pulled down to a logic zero based on a logical function of programmed memory elements. Thus, the present invention guarantees predictable output characteristics when a configurable system logic device is being programmed.
The present invention further provides a delay circuit that programmably varies the amount of the delay through the circuit. Specifically, the present invention provides a signal propagation delay from a programmable input/output (PIO) to an internal routing structure. As a result, zero hold time for an arbitrary input register relative to a fixed global clock is achieved.
In accordance with another aspect of the present invention, an OR gate combines the inputs from a horizontal routing channel and a vertical routing channel and provides the combined signal to the data input of an output register. This use of the OR gate allows one test configuration during production testing to test two input signals into the regist
Cheung Edmond Y.
Fox Brian
Papaliolios Andreas
Winegarden Steven P.
Blakely , Sokoloff, Taylor & Zafman LLP
Tran Anh
Triscend Corporation
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