Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-02-08
2005-02-08
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S021000
Reexamination Certificate
active
06853213
ABSTRACT:
Disclosed is an input/output circuit having a terminating circuit that contributes to a smaller chip area. The input/output includes an output buffer having a first series circuit, which comprises a first transistor and a resistor and a second series circuit, which comprises a second transistor and a resistor, connected in parallel between a high-potential power supply and an input/output pin, as well as a third series circuit, which comprises a third transistor and a resistor and a fourth series circuit, which comprises a fourth transistor and a resistor, connected in parallel between the input/output pin and a low-potential power supply. The input/output circuit further includes an input buffer having an input terminal connected to the input/output pin, and a control circuit which, at the time of a signal output, performs control for supplying a signal, which is obtained by inverting the logic of output data, to gates of the first to fourth transistors, and which, at the time of a signal input, performs control for supplying the gates of the first and third transistors with the high-potential power supply voltage and low-potential power supply voltage, respectively, and the gates of the second and fourth transistors with the low-potential power supply voltage and high-potential power supply voltage, respectively.
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patent: 6054881 (2000-04-01), Stoenner
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patent: 9-83411 (1997-03-01), None
Cho James H.
Elpida Memory Inc.
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