Input/output cells for a double data rate (DDR) memory...

Details Input/output cells for a double data rate (DDR) memory... Input/output cells for a double data rate (DDR) memory...

2006-06-13

2006-06-13

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000

Reexamination Certificate

active

07062625

ABSTRACT:
An interface for sending write data, write control signals and write data between a memory controller and a double data rate (DDR) memory with the appropriate timing relationships so that the write data can be reliably written in the DDR memory. Also, an interface for reliably capturing read data received from the DDR memory during a read operation.

REFERENCES:
patent: 6452865 (2002-09-01), Wolford
patent: 6493285 (2002-12-01), Wolford
patent: 6529993 (2003-03-01), Rogers et al.
patent: 6571308 (2003-05-01), Reiss et al.
patent: 6593575 (2003-07-01), Fries
patent: 6665230 (2003-12-01), Shrader et al.
patent: 6671211 (2003-12-01), Borkenhagen et al.
DDR SDRAM Functionality and Controller Read Data Capture, DesignLine, Micron Technology Inc. vol. 8, Issue 3, pp. 1-24 3Q99.

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