Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-29
2004-04-13
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06721933
ABSTRACT:
Japanese Patent Application No. 2000-343309, filed Nov. 10, 2000, is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to an I/O cell placement method and a semiconductor device using the same.
BACKGROUND
In some semiconductor devices which include a semiconductor chip of silicon or the like where an integrated circuit is formed, input/output cells (hereinafter called “I/O cells”) which have an interface capability with respect to an external circuit are arranged along the outer peripheral portion of the chip. In this case, pads as electrodes to electrically connect to the external circuit may be placed in a portion located further outward of the I/O cells. The individual pads are electrically connected to the corresponding I/O cells. The I/O cells include a circuit for connecting the integrated circuit formed in the semiconductor chip to the external circuit.
SUMMARY
One aspect of the invention relates to an I/O cell placement method for placing I/O cells which are included in a semiconductor device electrically connected to a given external device and have electric interface function with respect to the external device, the method comprising a step of placing at least two columns of I/O cells from an outer peripheral portion of a chip toward a chip core portion in such a manner that a longitudinal direction of each of the I/O cells is parallel to an outer peripheral portion.
Another aspect of the invention relates to a semiconductor device electrically connected to a given external device, comprising at least two columns of I/O cells which are placed from an outer peripheral portion of a chip toward a chip core portion in such a manner that longitudinal direction of the I/O cell is parallel to the outer peripheral portion and have an electric interface function with respect to the external device.
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Oliff & Berridg,e PLC
Seiko Epson Corporation
Thompson A. M.
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