Input-output bus interface to bridge different process...

Details Input-output bus interface to bridge different process... Input-output bus interface to bridge different process...

1999-11-30

2004-08-17

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S068000, C326S086000

Reexamination Certificate

active

06777975

ABSTRACT:

FIELD
The present invention relates to electronic systems, and more particularly, to a bus.
BACKGROUND
A GTL (Gunning Transceiver Logic) bus is well-known, where an example of an electronic system utilizing a GTL bus having nMOSFET (n-Metal Oxide Semiconductor Field Effect Transistor) driver
102
is illustrated in FIG.
1
. In the example of
FIG. 1
, two agents are connected to transmission line
104
to receive signals from nMOSFET driver
102
. An agent may be a microprocessor, memory device, or any other electronic device for sending or receiving signals along transmission line
104
. Resistors R
T
are termination resistors to reduce reflections at the ends of transmission line
104
, and are connected to a voltage source providing a termination voltage V
TT
. Resistor R
ESD
is a resistor to reduce the probability of electrostatic discharge damage to nMOSFET driver
102
, and may not be needed for some applications. The gate of nMOSFET driver
102
is driven according to a digital data signal so as to switch nMOSFET driver
102
ON and OFF to drive transmission line
104
.
The ideal (quiescent or steady state) voltage of transmission line
104
is in the range [V
TT
−V
SW
, V
TT
], where the voltage swing V
SW
is given by V
SW
=V
TT
[(R
T
/2)/(R
ONn
+R
ESD
+R
T
/2)] and where R
ONn
is the ON resistance of nMOSFET driver
102
. Because of impedance mismatch due to mismatches between nMOSFET driver
102
, termination resistor R
T
, and transmission line
104
, as well as stubs
106
and other artifacts, the actual signal voltage propagating along transmission line
104
will have over-shoots and under-shoots outside the ideal or quiescent voltage range. Note that in the above lumped-parameter equation for V
SW
, the resistance R
ESD
adds to the resistance R
ONn
. When R
ESD
is present, nMOSFET driver
102
needs to be designed with smaller R
ONn
than when R
ESD
is not present in order to maintain the same voltage swing on transmission line
104
. However, reducing R
ONn
increases the size of nMOSFET driver
102
, which increases the impedance mismatch.
In addition to distributing the core voltage V
CC
in an electronic system, GTL busses also require distributing the termination voltage V
TT
, which may result in added system cost due to extra motherboard power planes, wiring, pins, etc. Furthermore, with new process technologies allowing for smaller core voltages than in the past, signal over-shoots above V
TT
may be too large for the oxide thickness of new process technologies. This problem may be alleviated by lowering the termination voltage, but then the voltage range [V
TT
−V
SW
, V
TT
] of transmission line
104
will be shifted, which may require a re-design of agents connected to the transmission line. Embodiments of the present invention address some or all of these problems.
SUMMARY
Embodiments of the present invention are directed to a bus in which a terminated transmission line is excited by a pMOSFET, where the transmission line is terminated by connecting at least one termination device between the transmission line and ground. In one embodiment, the pMOSFET has its drain connected to the transmission line and its source biased to a core voltage V
CC
.


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EETimesonline, Semiconductor News, “Fairchild Touts GTLP for Telecom Busses”, 1 pg., Feb. 17, 1999.

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