Input/output buffer circuit having reduced power consumption

Details Input/output buffer circuit having reduced power consumption Input/output buffer circuit having reduced power consumption

1996-03-28

1998-04-14

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Current driving

326 29, 326 56, 326 86, H03K 190175

Patent

active

057397015

ABSTRACT:
There are provided an input/output buffer circuit having a reduced power consumption, and an electronic equipment using these buffer circuits. An input buffer is located on an input line while an output buffer is disposed on an output line. Each of the buffers is connected to an input/output line having input/output terminals. A latch circuit is connected to the input/output line and is switched between a first ON state in which the latch circuit is latchable and a first OFF state in which an output end of the latch circuit is in high impedance by a first control signal from a first control terminal. The output buffer is switched between a second ON state in which the output buffer can output a signal and a second OFF state in which an output end of the output buffer is in high impedance by a second control signal from a second control terminal. The first and second control signals may be common, or the second control signal may be generated by delaying it relative to the first control signal at a delay circuit.

REFERENCES:
patent: 4617476 (1986-10-01), Dalrymple
patent: 4766336 (1988-08-01), Warner
patent: 4992679 (1991-02-01), Takata et al.
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 5291080 (1994-03-01), Amagasaki
patent: 5498976 (1996-03-01), Hwang

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