Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-04-18
2004-08-24
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S058000, C326S083000, C326S081000, C327S534000, C327S537000
Reexamination Certificate
active
06781414
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input/output buffer circuit. More particularly, it relates to an input/output buffer circuit wherein an input signal with voltage higher than its power source voltage is inputted to an input/output terminal
2. Description of Related Art
In recent years, fine structuralizing technology with respect to CMOS-structured semiconductor integrated circuits (referred as LSI hereinafter) has advanced and driving power source voltage level of LSI has been lowering progressively. However, lowering degree of driving power source voltage level differs due to product diversity. Therefore, a plurality of LSI power source different in voltage must be combined when structuring a system. It would be preferable if terminals of LSI power source different in voltage could be connected directly. In case connecting input/output terminals, there must be considered an aspect such that an input signal with voltage amplitude different from voltage amplitude of an output signal may be inputted. Accordingly, even if a signal with voltage amplitude same as or higher than voltage amplitude of power source voltage is inputted from an external, it must be secured that an unnecessary current path is never formed between the external and the power source voltage. Therefore, various circuit systems have been proposed until now.
An input/output buffer circuit
100
shown in
FIG. 6
as a first prior art is a circuit carried by the 1992 October Edition of NIKKEI MICRODEVICES (pp.83-88).
An input/output mode switching signal CNT and an output data signal DOUT are inputted to a two-input NAND logic gate
11
and to a two-input NOR logic gate
12
. An output terminal of the two-input NAND logic gate
11
is connected to a gate terminal G
2
of a PMOS transistor P
2
which is a driving transistor arranged at high voltage side through a transfer gate
3
. An output terminal of the two-input NOR logic gate
12
is connected to a gate terminal of an NMOS transistor N
2
which is a driving transistor arranged at low voltage side. A signal is outputted from an input/output terminal BUS by the PMOS transistor P
2
and the NMOS transistor N
2
.
Furthermore, to a point between gate terminal G
2
of the PMOS transistor P
2
and the input/output terminal BUS, there is connected a PMOS transistor P
3
a gate terminal of which is connected to power source voltage VDD. Thereby, this system works such that the gate terminal G
2
of the PMOS transistor P
2
is clamped together with input signal voltage VBUS so that the PMOS transistor P
2
should be kept non-conductive in case an input signal with voltage higher than the power source voltage VDD is inputted from the input/output terminal BUS.
Furthermore, a PMOS transistor P
1
and an NMOS transistor N
1
constitute the transfer gate
3
. The input/output terminal BUS is connected to a gate terminal of the PMOS transistor P
1
and a gate terminal of the NMOS transistor N
1
is connected to the power source voltage VDD. In case an input signal with voltage higher than power source voltage VDD is inputted from the input/output terminal BUS, this system sets the NMOS transistor N
1
and the PMOS transistor P
1
in an off state, whereby a path leading to an output terminal of the NAND logic gate
11
from the input/output terminal BUS by way of the PMOS transistor P
3
is blocked.
With respect to a PMOS transistor P
10
, its gate terminal, drain terminal, and source terminal are connected to the input/output terminal BUS, power source voltage VDD, and N-well NW for the PMOS transistor P
1
through P
3
, respectively. The connection of the source terminal and the N-well NW constitutes an N-well voltage control circuit VFM
1
which adjusts voltage of the N-well NW depending on voltage inputted from the input/output terminal BUS. Furthermore, in case an input signal with high voltage is inputted from the input/output terminal BUS, NMOS transistors N
3
and N
4
are arranged to protect an NMOS transistor N
2
and an input buffer circuit
4
from high voltage.
Here will be considered a case such that an input signal with voltage same as or higher than voltage obtained by adding threshold voltage Vthp of PMOS transistor to the power source voltage VDD is applied to the input/output terminal BUS of the input/output buffer circuit
100
. Input signal voltage VBUS from the input/output terminal BUS is applied to the gate terminal of the PMOS transistor P
10
, whereby bias of the power source voltage VDD toward the N-well NW is blocked. Through a PN-junction constituted by drain terminals of the PMOS transistors P
2
and P
3
to which the input/output terminal BUS is connected, voltage of the N-well NW under this state approximates a value of the input signal voltage VBUS. As a result, a junction of the N-well NW and the source terminals of the PMOS transistors P
2
and P
10
to which the power source voltage VDD is connected turns into a reverse bias state and current-flow toward the power source voltage VDD through the PMOS transistors P
2
and P
10
is blocked.
Furthermore, since the power source voltage VDD is applied to the gate terminal of the PMOS transistor P
3
the drain terminal of which is connected to the input/output terminal BUS, the PMOS transistor P
3
becomes conductive and the gate terminal G
2
of the PMOS transistor P
2
is biased to the input signal voltage VBUS. Thereby, the PMOS transistor P
2
is kept in an off state and a current path running through the PMOS transistor P
2
is blocked.
Furthermore, since the gate terminal of the transfer gate
3
is connected to the input/output terminal BUS, the PMOS transistor P
1
is kept in an off state. On the other hand, since its drain terminal is connected to the terminal G
2
biased to the input signal voltage VBUS, the NMOS transistor N
1
the gate terminal of which is connected to the power source voltage VDD operates with a saturation region. Accordingly, voltage same as or higher than the power source voltage VDD is never applied to a connection terminal to the NAND logic gate
11
through the transfer gate
3
, whereby a current path leading to the power source voltage VDD through the PMOS transistors constituting the NAND logic gate
11
is not established.
As described, the input/output buffer circuit
100
directed to the first prior art prevents current from flowing from the input/output terminal BUS to the power source voltage VDD in case an input signal with voltage same as or higher than voltage obtained by adding the threshold voltage Vthp of PMOS transistor to the power source voltage VDD is applied to the input/output terminal BUS.
FIG. 7
shows an input/output buffer circuit
200
directed to a second prior art. In the input/output buffer circuit
200
, there is not established a direct connection between an input/output terminal BUS and a gate terminal G
1
of a PMOS transistor P
1
which constitutes a transfer gate
3
corresponding to the first prior art. Instead, the input/output terminal BUS and the gate terminal G
1
are connected to each other through a PMOS transistor P
4
a gate terminal of which is connected to the power source voltage VDD. Furthermore, the gate terminal G
1
is connected to ground voltage through an NMOS transistor N
5
. An input/output mode switching signal CNT inverted by an inverter logic gate
6
is inputted to a gate terminal of the NMOS transistor N
5
.
In the input/output buffer circuit
200
, high-voltage proof elements are used for an NMOS transistor N
2
and an input stage of and an input buffer circuit
4
. Therefore, the NMOS transistors N
3
and N
4
arranged as protection from high voltage in the input/output buffer circuit
100
are not required in the second prior art. That is, the NMOS transistor N
2
and the input buffer circuit
4
are directly connected to the input/output terminal BUS.
Furthermore, instead of the N-well voltage control circuit VFM
1
in the input/output buffer circuit
100
, an N-well voltage control circuit VFM
2
is arranged in the input/output buffer circ
Arent & Fox PLLC
Chang Daniel D.
Fujitsu Limited
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