Input/output buffer

Details Input/output buffer Input/output buffer

2005-03-01

2005-03-01

JeanGlaude, Jean (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000

Reexamination Certificate

active

06861874

ABSTRACT:
An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.

REFERENCES:
patent: 5635861 (1997-06-01), Chan et al.
patent: 5729157 (1998-03-01), Monk et al.
patent: 5880602 (1999-03-01), Kaminaga et al.
patent: 5973511 (1999-10-01), Hsia et al.
patent: 6300800 (2001-10-01), Schmitt et al.

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