Input/output architecture for efficient configuration of...

Details Input/output architecture for efficient configuration of... Input/output architecture for efficient configuration of...

2000-09-21

2003-02-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

06518787

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to programmable Input/Output (I/O) cells as part of a configurable system on a chip, and more specifically to an improved method of configuring the I/O cells.
BACKGROUND
Today some electronic systems and devices contain a configurable system on a chip (CSOC). A description of CSOC architecture is shown in
FIG. 2
of Patent Cooperation Treaty, Patent Document No. WO 00/22546, published Apr. 20, 2000. A CSOC integrates a CPU, an internal system bus, programmable logic also referred to as configurable system logic (CSL), and various system resources all interconnected and communicating via the internal system bus on a single chip. Most CSOCs are comprised of core electronics (e.g. CPU, RAM, ROM, DMA, etc.) at their center and input/output electronics, or an I/O ring, at their periphery. The I/O cells (in this case programmable I/Os (PI/Os)) contain a bonding pad with an input buffer and an output buffer. The pad can be used as an input pin, an output pin, or a bidirectional pin. The physical location of the PI/O pad ring to the rest of the chip is shown in FIG.
1
.
FIG. 1
is a diagram depicting PI/O ring architecture. Shown in the chip
100
of
FIG. 1
are PI/O control and configuration logic
105
, a plurality of PI/O memory cells in a PI/O ring
110
placed around the edges of the chip, Read/Write control signals line
115
, Read/Write data bus
125
, and embedded resources
130
and chip logic
135
at the center of the chip. The PI/O ring is typically comprised of several (sometimes hundreds) of PI/O cells, one for each external signal of the system. The number of PI/O pins depends on the base device type and the package. The PI/O ring may contain several I/O cell types (e.g. input cells, output cells, tristate output cells and bidirectional cells), one for each external signal type. Typically, each PI/O contains a bidirectional I/O buffer that is programmable. The user decides the use of each pin as input, output, or bidirectional. The PI/O cells can be customized by the embedded system through configuration. The PI/O cells interface with signals from the embedded resources or the CSL. When a PI/O cell interfaces with embedded resources it is called a system pin. The embedded system controls the function and configuration of a system pin. Users can configure the electrical characteristics of a system pin, but cannot alter the function of a system pin (i.e. the user cannot change the direction, input, output, or bi-directional, of a system pin). When a PI/O cell interfaces with CSL, it is called a general PI/O pin. Users can configure both the functional and electrical characteristics of a general PI/O pin. Each PI/O cell contains a configuration register to customize the functional and electrical characteristics. For example each output buffer can be configured with high or low slew-rate. Slew-rate control provides a tradeoff between low-noise and high-speed performance. Depending on the amount of external memory connected to the device, drive or slew characteristics of the system I/O buffers might need to be modified.
The user can also select between two levels of drive current strength independent of the slew-rate. The combination of drive current strength and slew-rate control allows different grades of speed and noise immunity.
Another characteristic of which user configuration is desirable is internal weak input resistance. I/O cells of different integrated circuits (ICs) can have different electronic operating characteristics. When two or more I/O cells of different ICs are connected together through a media, the connecting net often requires some form of biasing (pull-up or pull-down) and/or termination to ensure the error-free operation of all the connected I/O cells or to guarantee no nets will be floating, providing noise immunity.
Other characteristics that can be configured include power-saving features used with the output enable and input enable during power down mode.
FIG. 2
describes the process by which a user configures the general PI/O pins. The process
200
shown in
FIG. 2
begins at operations
205
a
and
205
b
. In operation
205
a
, starting with the PI/O control and configuration logic
105
, the configuration control and data lines propagate write data through the entire ring in a counter-clockwise direction. At the same time the core logic generates individual select lines that are asserted to select the PI/O memory cells, operation
205
b
. In operation
210
each memory cell, in turn, receives the control and write data from the previous cell and propagates a buffered version to the next cell. The process continues around the entire ring until the data is stabilized. In operation
215
the write command is asserted and is propagated through the entire ring. Then, depending on which PI/O memory cells have been selected in operation
205
b
, the data will be written to the correct cell. The write command is then deasserted and propagates through the entire ring, operation
220
. As
FIG. 2
describes, writing to a PI/O memory cell is done in three steps (i.e. propagate data while selecting the PI/O memory cell, assert the write command, deassert the write command), and in each step the signals must propagate through the entire ring, therefore the configuration write time is 3TN where T is the time to propagate through the ring and N is the number of PI/O cells to be programmed. The process to read from a PI/O memory cell is faster, as there is no write data propagation. The reading is done in one step, the read command propagates throughout the entire ring while the read data from the selected cell propagates in the same direction from the cell. Because the read command must be propagated through the entire ring the time for the process is TN. Reading is not as time critical as writing because reading is useful mainly for debugging purposes.
SUMMARY OF THE INVENTION
A device is described having a plurality of programmable input/output memory cells configured in corresponding segments. Each cell of a segment shares a select line with a cell of each remaining segment. Control logic is coupled to the programmable input/output memory cells and data is propagated at approximately the same time from the control logic through each of the corresponding segments of input/output memory cells. The invention discloses a more efficient method of configuring programmable I/O cells without increasing the area of the cell.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.


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