Input latency control circuit, a semiconductor memory device...

Details Input latency control circuit, a semiconductor memory device... Input latency control circuit, a semiconductor memory device...

2007-03-08

2009-08-25

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S233100, C365S230030

Reexamination Certificate

active

07580319

ABSTRACT:
An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal. The example input latency control circuit may include a master circuit configured to generate a column control signal and a first write address control signal based on an internal clock signal, a write command signal and a write latency signal, at least one column slave circuit configured to gate a first address signal in a pipeline mode to generate a column address signal in response to the column control signal and one of the first write address control signal and a second write address control signal and at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address signal in response to the column control signal and at least one of the first and second write address control signals.

REFERENCES:
patent: 5892730 (1999-04-01), Sato et al.
patent: 5978884 (1999-11-01), Yamaguchi et al.
patent: 6212126 (2001-04-01), Sakamoto
patent: 7397727 (2008-07-01), Schnell et al.
patent: 2008/0123452 (2008-05-01), Kim
patent: 2004-206751 (2004-07-01), None
patent: 1022030046128 (2003-06-01), None
patent: 1020040043700 (2004-05-01), None
patent: 1020040074283 (2004-08-01), None
patent: 1020040107706 (2004-12-01), None

Affiliated with

Also associated with

Rating

Input latency control circuit, a semiconductor memory device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input latency control circuit, a semiconductor memory device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input latency control circuit, a semiconductor memory device... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4120178