Input interface level determiner for use in a memory device

Details Input interface level determiner for use in a memory device Input interface level determiner for use in a memory device

1998-08-14

1999-06-29

Nelms, David

Static information storage and retrieval

Read/write circuit

Including signal comparison

36518909, G11C 1604

Patent

active

059177594

ABSTRACT:
In order to determine input interface levels of a memory device at the time when operating the device, a constant voltage generator is provided to generate a constant voltage. A comparator, coupled to receive the constant voltage, compares the constant voltage with either first or second reference voltage. The first and second reference voltages are selectively applied to said comparator via an external pin of the memory device. A connection controller is coupled to receive a comparison result which has been generated from the comparator. The connection controller, in response to the comparison result related to the first reference voltage, establishes electrical connection between the external pin and an input buffer provided in the memory device. For example, the first reference voltage is used to operate the memory device at Stub Series Terminated Logic (SSTL) levels. On the other hand, the connection controller, in response to the comparison result related to the second reference voltage, prevents electrical connection between the external pin and the input buffer. Therefore, the connection controller allows the memory device to operate at Low Voltage Transistor-Transistor Logic (LVTTL) levels by way of example.

REFERENCES:
patent: 5331219 (1994-07-01), Nakamura
Standard of Electronic Industries Association of Japan; Stub Series Terminated Logic For 3.3 Volts (SSTL.sub.- 3); Mar. 1996.

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