Input delay control

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices

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Details

257724, 257786, 257773, H01L 2334

Patent

active

057194459

ABSTRACT:
Signal propagation times in circuit paths are matched to compensate for signal delays due to differences in the physical parameters, such as lengths, of the circuit paths. This is accomplished by adjusting the length of lead lines and by the addition of resistors in series with shorter lead lines in a chip or die. In a chip with an active device, such as logic, having multiple input lines, the lines are divided into long lines and short lines. All long lines are laid out so as to have the same length and to use the least amount of chip surface area. Similarly, all short lines are laid out on the chip so as to have the same length while using the least amount of chip surface area. With all the short lines having the same propagation time difference relative to all the long lines, the same resistive element is added to all the short lines to effect the same RC delay in signal propagation on the short lines so as to match the signal propagation time on the short lines with that on the long lines.

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patent: 5305320 (1994-04-01), Andrews et al.
patent: 5345449 (1994-09-01), Buckingham et al.
patent: 5381416 (1995-01-01), Vartti
patent: 5416918 (1995-05-01), Gleason et al.
patent: 5463252 (1995-10-01), Jones et al.
patent: 5473195 (1995-12-01), Koike
patent: 5523620 (1996-06-01), Eytcheson et al.

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