Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2009-05-11
2011-10-18
Bonzo, Bryce (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
08041992
ABSTRACT:
Techniques are generally described for correcting computation errors via input compensation and/or input overcompensation. In various examples, errors of a computation may be detected, and input compensation and/or overcompensation to correct the errors may be created. The disclosed techniques may be used for power and/or energy minimization/reduction, and debugging, among other applications. Other embodiments and/or applications may be disclosed and/or claimed.
REFERENCES:
patent: 5179695 (1993-01-01), Derr et al.
patent: 6567937 (2003-05-01), Flores et al.
patent: 6782345 (2004-08-01), Siegel et al.
patent: 6849174 (2005-02-01), Hada et al.
patent: 7340643 (2008-03-01), Grochowski et al.
patent: 7480838 (2009-01-01), Wilkerson et al.
patent: 7516358 (2009-04-01), Haefliger et al.
patent: 7671627 (2010-03-01), Somani et al.
patent: 2004/0078410 (2004-04-01), Porten et al.
patent: 2005/0022094 (2005-01-01), Mudge et al.
patent: 2006/0123308 (2006-06-01), Eslick et al.
patent: 2007/0150784 (2007-06-01), Pan et al.
patent: 2008/0082598 (2008-04-01), Dapper et al.
patent: 2008/0091990 (2008-04-01), Bruce et al.
patent: 2008/0109679 (2008-05-01), Wright et al.
patent: 2009/0218178 (2009-09-01), Lence-Barreiro
patent: 2009/0282293 (2009-11-01), Martch et al.
International Search Report and Written Opinion, issued in International Application No. PCT/US2010/033608, mailed Sep. 8, 2010, 8 pages.
Austin et al., “Making Typical Silicon Matter with Razor,” Computer, Mar. 2004, vol. 37, No. 3, pp. 57-65.
Bower et al., “A Mechanism for Online Diagnosis of Hard Faults in Microprocessors,” Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2005, 12 pages.
Chandrakasan et al., “Optimizing Power Using Transformations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 1995, vol. 14, No. 1, pp. 12-31.
Ernst et al., “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation,” Proceedings of the 36th International Symposium on Microarchitecture, Dec. 2003, 12 pages.
Kirovski et al., “Cut-Based Functional Debugging for Programmable Systems-on-Chip,” IEEE Transactions on Very Large Scale Integration (VSLI) Systems, Feb. 2000, vol. 8, No. 1, pp. 40-51.
Kirovski et al., “Improving the Observability and Controllability of Datapaths for Emulation-Based Debugging,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. 1999, vol. 18, No. 11, pp. 1529-1541.
Koushanfar et al., “Symbolic Debugging of Embedded Hardware and Software,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Mar. 2001, vol. 20, No. 3, pp. 392-401.
Li et al., “Spin Detection Hardware for Improved Management of Multithreaded Systems,” IEEE Transactions on Parallel and Distributed Systems, Jun. 2006, vol. 17, No. 6, pp. 1-14.
Mehrara et al., “Low-cost Protection for SER Upsets and Silicon Defects,” Proceedings of the conference on Design, Automation and Test, Apr. 2007, pp. 1146-1151.
Potkonjak et al., “Maximally and Arbitrarily Fast Implementation of Linear and Feedback Linear Computations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 2000, vol. 19, No. 1, pp. 30-43.
Powell et al., “Heat-and-Run: Leveraging SMT and CMP to Manage Power Density Through the Operating System,” Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2004, pp. 260-270.
Sanz et al., “System-level Process Variability Compensation on Memory Organizations of Dynamic Applications: A Case Study,” Proceedings of the 7th International Symposium on Quality Electronic Design, Mar. 2006, 7 pages.
Shyam et al., “Ultra Low-Cost Defect Protection for Microprocessor Pipelines,” Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2006, pp. 73-82.
Bonzo Bryce
Schwabe Williamson & Wyatt P.C.
Technology Currents LLC
LandOfFree
Input compensated and/or overcompensated computing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Input compensated and/or overcompensated computing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input compensated and/or overcompensated computing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4268266