Input circuit with non-delayed time blanking

Details Input circuit with non-delayed time blanking Input circuit with non-delayed time blanking

2001-06-27

2003-04-22

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S093000, C327S217000

Reexamination Certificate

active

06552570

ABSTRACT:

TECHNICAL FIELD
This disclosure relates generally to integrated circuits, and in particular but not exclusively, relates to input circuits.
BACKGROUND
A typical integrated circuit includes input circuits to receive signals from other parts of the integrated circuit and output them with “restored” voltage levels and appropriate driving current for circuitry receiving the output signal of the input circuit. As is well known, a variety of sources may inject noise into the signal received by the input circuit. For example, sources include ringing caused by mismatched output drivers or interconnect impedance, signal cross-coupling, and power supply noise. This noise can cause an input circuit to improperly output the received signal.
One conventional solution to this noise problem is to design the input circuits with hysteresis (e.g., having a trip point for low-to-high transition that is higher than the trip point for a high-to-low transition of the input signal). However, this solution is ineffective against noise that causes the signal to exceed one of the trip points.


REFERENCES:
patent: 5319678 (1994-06-01), Ho et al.
patent: 5502409 (1996-03-01), Schnizlein et al.
patent: 5539337 (1996-07-01), Taylor et al.
patent: 6218879 (2001-04-01), Kilpatrick
M.S. Ghausi, Electronic Devices and Circuits, 1985, pp. 638 and 639, CBS College Publishing, New York.

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