Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-12-06
2001-09-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000, C326S068000, C326S073000
Reexamination Certificate
active
06294932
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input circuit, an output circuit and an input-output circuit for transmitting a signal between semiconductor devices connected through transmission lines and more particularly to an input circuit, an output circuit and an input-output circuit (hereinafter referred to as an interfacing circuit) enabling signal transmission (or signal interfacing) to be performed at high speed and with less power consumption.
2. Description of the Related Art
In recent years, small-amplitude interfacing specifications including GTL (Gunning Transceiver Logic), CTT (Center Tapped Termination), LVDS (Low Voltage Differential Signaling), PECL (Pseudo Emitter Coupled Logic), PCML and the like are increasingly used for transmitting signals through transmission paths such as bus lines between semiconductor devices composed of two or more integrated circuits.
In the conventional signal transmission, a signal used for the transmission has an amplitude being near to that of a supply voltage being applied to integrated circuits. However, in the interfacing specifications described above, a signal having a specified amplitude which is converted to a small level is transmitted. Taking a case of CMOS (Complementary Metal Oxide Semiconductor) interfacing as an example, an amplitude of a signal being transmitted by the conventional method is generally about 5 V or 3 V, which is approximately equal to that of a supply power voltage applied to integrated circuits or the like.
However, for example, in the case of the LVDS (Low Voltage Differential Signaling) interfacing specifications, an amplitude of a signal to be transmitted is as small as about 0.3 V. In the case of the PECL interfacing specifications, it is about 0.6V.
The reason for making an amplitude of a transmission signal small is that it is clearly attributable to an increase of the transmission speed, lowering of the power consumption and reduction of noise.
In the case of the PECL interfacing specifications, for example, a high-level small-amplitude signal can be generated by allowing a specified current to flow, in an output circuit, through a terminating resistor to a terminating voltage source and thereby producing electromotive force with a specified terminating resistor, while a low-level small-amplitude signal can be generated by allowing a specified current to flow, in an output circuit, through a resistor from a terminating voltage source and thereby producing electromotive force with a specified terminating resistor. Accordingly, a high-level small-amplitude signal to be produced has a voltage level being lower by about 0.3 V with respect to the terminating voltage while a low-level small-amplitude signal has a voltage level being lower by about 0.3 V as well. As a result, a signal having an amplitude of about 0.6 V is produced.
In general, two methods are available for transmitting such small-amplitude signals, one being a single-phase transmission system and the other being a differential-phase transmission system. In the case of the single-phase transmission system, only one small-amplitude signal is used for signal transmitting. On the other hand, in the case of the differential-phase transmission system, in addition to one small-amplitude signal being equivalent to that used by the single-phase transmission system, another small-amplitude signal being in inverse phase is transmitted at the same time, i.e., two small-amplitude signals are simultaneously transmitted.
When a signal is received by the single-phase transmission system, to one of two input terminals mounted on a receiving circuit is supplied a reference voltage being near to a center voltage of an amplitude of the signal and to the other input terminal is inputted the transmission signal, and if the transmission signal having a voltage being higher than the reference voltage is supplied, the transmission signal is judged to be a high-level signal and if the transmission signal having a voltage being lower than the reference voltage is supplied, the signal is judged to be a low-level signal.
When a signal is received by the differential-phase system, two small-amplitude signals including one not being in inverse phase and the other being in inverse phase are transmitted simultaneously and these two signals are inputted to two input terminals mounted on the receiving circuit as they are. If the voltage of the signal inputted to an inversion-phase input terminal is higher than that of the signal inputted to an positive-phase input terminal, the signal is judged to be high, and if the voltage of the signal inputted to the inversion-phase input terminal is lower than that of the signal inputted to the positive-phase input terminal, the signal is judged to be low. The description hereafter is made according to an example using the differential-phase input terminal.
FIG. 7
is a schematic diagram showing one example of a conventional input-output circuit. As shown in
FIG. 7
, in the input-output circuit, a sending (controlling) integrated circuit
1
is connected through transmission lines
4
and input terminals IN and INB to a receiving (controlled) integrated circuit
2
. The integrated circuit
1
has an output circuit
3
adapted to convert, for example, logic signals inputted from an inputting circuit (not shown) or logic signals or the like used to control the integrated circuit
2
, to small-amplitude signals and to output the converted signals. The integrated circuit
2
has an input circuit
5
adapted to amplify small-amplitude signals inputted from the integrated circuit
1
to a predetermined amplitude level and a CMOS internal circuit
6
mounted on the same chip as the input circuit
5
is mounted and operated in accordance with a signal fed from the input circuit
5
. Each line of the transmission lines
4
is connected to each of terminating resistors Rt and is terminated at a terminating voltage (Vtt) with these terminating resistors Rt. Moreover, there are some interfacing specifications where the terminating resistor Rt is used, however, the terminating voltage Vtt is not applied.
FIG. 8
is a schematic diagram showing one specific example of a conventional input circuit. This conventional circuit is adapted to convert small-amplitude signals (i.e., logic signals or the like to control the CMOS internal circuit
6
) fed through the transmission lines
4
from the sending (controlling) integrated circuit
1
to a signal having a predetermined amplitude (VDD full-swing amplitude).
Referring to
FIG. 8
, signals supplied from the transmission lines
4
are fed to each of gates of p-chanel MOS transistors (hereinafter referred simply to as a pMOS transistor) P
1
and P
2
constituting an amplifying circuit
21
of the input circuit and the signal amplified by the amplifying circuit
21
is fed through a NodeA to an inverter circuit
22
, and the logic signal that has not yet been converted to a small-amplitude signal is fetched from the inverter circuit
22
by the sending (controlling) integrated circuit
1
. Moreover, the amplifying circuit
21
and the inverter circuit
22
are formed on the same integrated circuit (a chip).
The amplifying circuit
21
is comprised of a constant current circuit II, pMOS transistors P
1
and P
2
, and nMOS transistors N
1
and N
2
. A drain of the pMOS transistor P
1
is connected to a drain of the nMOS transistor N
2
and a source of the nMOS transistor N
2
is connected to a predetermined reference potential point GND of the receiving (controlled) integrated circuit
2
. Similarly, a drain of the pMOS P
2
is connected to a drain of the nMOS transistor N
1
and a source of the nMOS transistor N
1
is connected to the reference potential point GND. Moreover, the drain of the nMOS transistor N
1
(the drain of the pMOS transistor P
2
) is connected to gates of the nMOS transistor N
1
and the nMOS transistor N
2
, and drains of the pMOS transistor P
1
and the pMOS transistor P
2
are connected through the constant current circuit II to a p
McGuireWoods LLP
NEC Corporation
Tokar Michael
Tran Anh Q.
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