Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-12-10
2002-04-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S057000, C327S069000
Reexamination Certificate
active
06366126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input circuit, an output circuit, and an input/output circuit and a signal transmission system using the same input/output circuit.
2. Description of the Related Art
There are two modes for transmitting logical signals by using small-amplitude transmission signals via a transmission line such as for example a dual bus line between a plurality of integrated circuits by using a communication transmission device, a computer, etc; a single-phase transmission mode and a differential transmission mode.
The single-phase transmission mode permits a small-amplitude signal utilized in signal transmission, to be transmitted via a dual bus line, while the differential transmission mode permits a small-amplitude signal equivalent to a transfer signal for the single-phase transmission mode to be transmitted via one line of the dual bus line and, at the same time, to permit a signal obtained by converting only the phase of the above-mentioned small-amplitude signal, to be transmitted via the other line of the dual bus line. The following will describe the differential transmission mode.
When such a differential transmission mode is used to transmit logical signals using the above-mentioned two signals via a dual bus line between a plurality of integrated circuits, an output circuit is employed which sends the logical signals onto these transmission lines. In a case where this output circuit is used to transmit logical signals, a logical signal to be transmitted (also called transmission signal) represents, respectively, a logical value “1” or “0” when one of the two transmission lines is of a high-level voltage and the other is of a low-level voltage and logical value “0” or “1” when one of the dual transmission line is of a low-level voltage and the other is of a high-level voltage. When an output circuit is outputting a logical value 1 or 0, it is said to be outputting a state 1 or a state 0 respectively.
In most cases, a voltage amplitude between a high level and a low level of those two output states has been of such a value of a supply voltage fed to integrated circuits.
In recent years, however, in more and more cases an extremely small amplitude of a signal is transmitted. In a case of a CMOS interface, for example, an amplitude of its conventional transmission signal has typically been about 5V or about 3V, which is nearly equivalent to a feeding supply voltage. As against this, in a case of for example a small-amplitude of signal transmission for an LVDS (Low Voltage Differential Signaling) interface, its signal amplitude in recent years is very small value of about 0.3V.
The reason why a signal amplitude is reduced to such a small value is that the reduction has large effects in for example improving a transmission rate and decreasing power dissipation and noise which occurs during signal transmission.
Thus, there is a need to use a low-amplitude interface output circuit for sending of a low-amplitude signal, in order to obtain the above-mentioned effects in an integrated circuit which has a basic concept of high-speed performance or low-power dissipation.
A low-amplitude interface output circuit which may meet such a need commonly uses as its output amplitude a small signal amplitude smaller than a supply voltage, in order to achieve high-speed, low-power dissipation, and low-noise performance. As such a low-amplitude interface output circuit are known, besides the above-mentioned LVDS, a configuration of GTL (Gunning Transceiver Logic), CTT (Center Tapped Termination), and PECL (Pseudo Emitter Coupled Logic). In the case of a PECL configuration of these low-amplitude interfaces for example, as against about 3V or about 5V as a value of its supply voltage, about a 0.6V is used as an amplitude of a signal which is employed. As a means for transferring such a small-amplitude signal, a terminating voltage source and a terminating resistor are utilized.
FIG. 4
shows an example of a small-amplitude interface circuit having this configuration.
This type of a low-amplitude interface circuit is used in a signal transmission system which uses integrated circuits. The low-amplitude interface circuit used, as shown in
FIG. 4
, in this signal transmission system is provided between its bus line
2
and input/output circuits
4
1
,
4
2
,
4
3
, and
4
4
of a plurality of semiconductor integrated circuits IC
1
, IC
2
, and IC
3
respectively. The bus line
2
consists of two lines L
1
and L
2
and is connected via terminating resistors RL
1
and RL
2
to a terminating power supply VS. This terminating power supply VS has V
TT
as its terminating voltage value. An input/output circuit
41
consists of an output circuit
4
1
O and an input circuit
4
1
I, which output circuit
4
1
O is supplied with an Enable signal EN from a CMOS internal circuit
5
1
. The output circuit
4
1
O, when supplied with the Enable signal EN, is set in an operative state (enabled state) and, when not supplied with it, is set in an inoperative state (disabled state) with its output being set in a high-impedance state simultaneously. Note here that a reference character IN shown in
FIG. 4
indicates an input signal sent from a CMOS internal circuit
51
to a CMOS internal circuit
41
O, while a reference character OUT indicates an output signal sent from the input circuit
41
I to the CMOS internal circuit
51
. Reference numerals IO
11
and IO
12
indicate respective output terminals of the input/output circuit
41
, which are connected to the two lines L
1
and L
2
of the bus line
2
.
Description of the input/output circuits
4
2
,
4
3
, and
4
4
is omitted here because they are of the same configuration as the input/output circuit
41
and provided with subscripts of
2
,
3
, and
4
at their reference numerals in the input and output circuits and the CMOS internal circuit.
An example of a known circuit used as these input/output circuits
4
1
,
4
2
,
4
3
, and
4
4
is shown in FIG.
5
. An input/output circuit
10
shown in
FIG. 5
comprises an output circuit
12
and an input circuit
14
. The input/output circuit
10
comes in the input/output circuit
41
for example. An output circuit
12
comprises: an input-signal supply circuit
16
(see
FIG. 6
) which inputs input signals; a reference voltage source
18
; a differential amplifier stage
20
; an enabled/disable-state switching circuit
22
(see FIG.
7
); a differential amplifier stage
24
; and an output stage
26
. The input circuit
14
comprises: a differential amplifier stage
42
; an output stage
44
; and a buffer B
1
.
The input-signal supply circuit
16
consists of a buffer
30
connected to an input terminal
28
, and an inverter
32
.
The differential amplifier stage
20
comprises n-channel type MOSFETs N
1
, N
2
, and N
3
and resistors R
1
and R
2
. A drain of the n-channel type MOSFET N
1
is connected via the resistor R
1
to the voltage source V
DD
and its source, to the n-channel type MOSFET N
3
at its drain. Also, a drain of the n-channel type MOSFET N
2
is connected via the resistor R
2
to the voltage source V
DD
and its source, to the n-channel type MOSFET N
3
at its drain. Also, a source of the n-channel type MOSFET N
3
is connected to the ground potential. A gate of the n-channel type MOSFET N
1
is connected is connected to the input-circuit supply circuit at its signal terminal
36
. A gate of the n-channel type MOSFET N
2
is connected to the input-signal supply circuit
16
at its output terminal
34
. A gate of the n-channel type MOSFET N
3
is connected to a reference-voltage source
18
at its output terminal. The n-channel type MOSFET N
3
constitutes a current source.
The resistor R
1
and the n-channel type MOSFET N
1
constitute one branch circuit of the differential amplifier stage
20
and the resistor R
2
and the n-channel type MOSFET N
2
, the other branch circuit of the differential amplifier stage
20
.
The enabled/disabled-state switching circuit
22
consist of an inverter
38
which has its input conne
Chang Daniel D.
NEC Corporation
Tokar Michael
Whitham Curtis & Christofferson, P.C.
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