Input circuit of semiconductor memory device for generating an i

Details Input circuit of semiconductor memory device for generating an i Input circuit of semiconductor memory device for generating an i

1996-11-26

1999-04-13

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 22, 326 98, H03K 190185

Patent

active

058942297

ABSTRACT:
In a DRAM, first and second P channel MOS transistors are connected in series between an output node of an NOR gate of an input buffer and a power supply line. The first P channel MOS transistor receives at its gate an external signal /EXT and the second P channel MOS transistor receives at its gate an inverted signal of an output enable signal OEM. In a data output period, the signal OEM attains to the "H" level and the second P channel MOS transistor is rendered conductive, and therefore, even when power supply potential Vcc lowers in the data output period, the output node can be sufficiently charged, and an internal signal /INT can be generated stably.

REFERENCES:
patent: 4891792 (1990-01-01), Hanamura et al.
patent: 5019724 (1991-05-01), McClure
patent: 5220205 (1993-06-01), Shigehara et al.
patent: 5309397 (1994-05-01), Amanai
patent: 5594361 (1997-01-01), Campbell
Millman et al., Microelectronics, McGraw-Hill, pp. 220 and 219, 1987.

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