Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1998-11-09
2001-04-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S113000, C326S057000
Reexamination Certificate
active
06211702
ABSTRACT:
FIELD OF THE INVENTION
1. Background of the Invention
The present invention relates to an input circuit for a microcomputer or the like.
2. Description of the Related Art
An input circuit for a microcomputer or the like in the prior art normally assumes a circuit structure such as that illustrated in
FIG. 11
to ensure that no through current flows into internal circuits when no input signal is provided from the outside such as at the time of a reset or in the low power consumption mode (stop mode) during which the clock is stopped, i.e., when the input terminal achieves a state of high impedance.
As illustrated in the figure, the input circuit provided between an input terminal
100
through which a signal is input from the outside and an internal input terminal
102
for inputting the signal to an internal circuit comprises a NAND gate
50
with one input end thereof connected to the input terminal
100
and a gate control signal E input to another input end thereof and an inverter
52
that inverts an output signal from the NAND gate
50
to input it to the internal input terminal
102
. The gate control signal E allows or prohibits the input of a signal which is to be input to the internal input terminal
102
from the outside via the input terminal
100
. When the gate control signal E is at high, the input of an input signal from the outside is allowed, whereas when it is at low, a state of high impedance is set for the NAND gate
50
to prohibit the input of the input signal. In addition, the NAND gate
50
is constituted so that any through current is prevented even when it is set in a state of high impedance by the gate control signal E.
As illustrated in
FIG. 12
, when the gate control signal E is set to low to prohibit signal input from the outside in the input circuit in the prior art, the internal input terminal
102
is fixed at low. However, when the signal level of the signal input to the input terminal
100
is at high before or after a period during which the signal input is prohibited, a change occurs in the signal level at the internal input terminal
102
which, depending upon the structure of an internal circuit which is connected to the internal input terminal
102
, sometimes results in an erroneous operation of an internal circuit.
SUMMARY OF THE INVENTION
A first object of the present invention, which has been completed by addressing the problem of the prior art discussed above, is to provide an input circuit in which a through current is prevented from flowing.
A second object of the present invention is to provide an input circuit with which any erroneous operation of a connected internal circuit can be prevented even when there is a change in the level of the input signal.
In order to achieve the objects described above, the input circuit according to the present invention is provided with an input gate which, in conformance with a control signal, is capable of allowing or prohibiting the output of a first signal that is based upon an input signal, and a latch circuit that holds the first signal and is capable of outputting a second signal based upon the first signal to an internal circuit.
This structure makes it possible to prevent any through current from flowing in the input circuit in an input-prohibited state in which the input of an input signal is prohibited at the input gate by the control signal.
In addition, since the signal level of the first signal is held by the latch circuit, any changes in the signal level of the second signal can be prevented. Thus, any erroneous operation of an internal circuit is prevented from occurring due to changes in the signal level of the second signal.
REFERENCES:
patent: 3739193 (1973-06-01), Pryor
patent: 3812384 (1974-05-01), Skorup
patent: 4451745 (1984-05-01), Itoh et al.
patent: 5132577 (1992-07-01), Ward
patent: 5404151 (1995-04-01), Asada
patent: 5739701 (1998-04-01), Oshima
patent: 5760608 (1998-06-01), Naffziger et al.
Rhyne, “Fundamentals of Digital Systems Design”, N.J. pp. 70-71, 1973.
Chang Daniel D.
Jones Volentine, L.L.C.
OKI Electric Industry Co., Ltd.
Tokar Michael
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