Input buffer with selectable threshold and hysteresis option

Details Input buffer with selectable threshold and hysteresis option Input buffer with selectable threshold and hysteresis option

2007-10-02

2007-10-02

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S040000, C327S205000, C327S407000

Reexamination Certificate

active

11340408

ABSTRACT:
An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

REFERENCES:
patent: 5327020 (1994-07-01), Ikeda
patent: 6377108 (2002-04-01), Kennedy et al.
patent: 6597224 (2003-07-01), Lin et al.
patent: 6906568 (2005-06-01), Lin et al.

Affiliated with

Also associated with

Rating

Input buffer with selectable threshold and hysteresis option does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input buffer with selectable threshold and hysteresis option, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input buffer with selectable threshold and hysteresis option will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3893178