Input buffer with level detector circuit

Details Input buffer with level detector circuit Input buffer with level detector circuit

1993-08-11

1995-05-02

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326121, 326 68, 327210, H03K 1716, H03K 1920

Patent

active

054122597

ABSTRACT:
An input buffer circuit with first and second inverters serially connected between an input terminal and an output terminal of the circuit. The input buffer circuit includes a level detector circuit for detecting that the level of a signal inputted to the input terminal is logically unsteady, and an output level holding circuit for detecting the level of a node where the first and second inverters are connected together and controlling the level of the node to maintain the level, when the level detector circuit detects that the level of the signal is logically unsteady.

REFERENCES:
patent: 4342065 (1982-07-01), Larson
patent: 4760283 (1988-07-01), Weaver
patent: 4806786 (1989-02-01), Valentine
patent: 5220205 (1993-06-01), Shigehara et al.
patent: 5256914 (1993-10-01), Boomer

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