Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-12-24
2004-11-02
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000
Reexamination Certificate
active
06812743
ABSTRACT:
TECHNICAL FIELD
The present disclosure relates to a semiconductor memory device, and more particularly, to an input buffer having a differential amplifier in the semiconductor memory device.
BACKGROUND
A semiconductor device is fabricated by semiconductor technologies such as a silicon wafer forming technology, and a logic design technology and so on. A final product through a semiconductor fabricating process is a chip of a plastic package type. The chip may be fabricated with different logics and functions according to a purpose for use thereof. Most of important semiconductor chips configuring an application system are assembled to a printed circuit board (PCB) and several driving voltages for driving the chips are supplied thereto.
All semiconductor devices including semiconductor memory operate according to input/output signals having specific purposes. Namely, operations of the semiconductor device are carried out in response to a combination signal of input/output signals. An output signal of a certain semiconductor device may be used as an input signal of another semiconductor device in the same system.
An input buffer is a part buffering a signal applied from an external circuit and providing the buffered signal into the semiconductor device and there is a static input buffer as the simplest type. The static input buffer consists of a PMOS transistor and an NMOS transistor connected in series between a power supply voltage and a ground voltage. The static input buffer has an advantage that the configuration is very simple, however, tolerance against a noise is weak, and, an input signal having large amplitude is required. Namely, the large amplitude between a logic high level and a logic low level of the input signal is required. Therefore, the static input buffer is not proper to be applied to a device, which the amplitude of input signals is small or a high operation frequency is required. Accordingly, an input buffer of a differential amplification type, which has a high tolerance against a noise and is easy to be applied to a high frequency, is suggested.
FIG. 1
is a schematic diagram illustrating a conventional input buffer of a differential amplification type. In particular, the input buffer
100
of the differential amplification type includes a differential amplification unit
11
and an internal buffer
12
. The differential amplification unit
11
compares an input signal applied to a positive terminal (+) thereof with a reference voltage signal applied to a negative terminal (−) thereof. The internal buffer
12
buffers an output from the differential amplification unit
11
and issues an internal signal INT.
FIG. 2
is a circuit diagram illustrating the differential amplification unit
11
in FIG.
1
. As shown, the differential amplification unit
11
includes a differential amplifier
11
A and an inverter
11
B. The differential amplifier
11
A includes a first NMOS transistor MN
1
, a second NMOS transistor MN
2
, a first PMOS transistor MP
1
, and a second PMOS transistor MP
2
to form a current mirror. The reference voltage Vref is applied to a gate of the first NMOS transistor MN
1
, and the input signal IN is applied to a gate of the second NMOS transistor MN
2
. The differential amplifier
11
A further includes a third NMOS transistor MN
3
, which is coupled between ground and the first and second transistors MN
1
and MN
2
. A buffer enable signal is applied to the gate of the transistor MN
3
for a bias. Third and fourth PMOS transistors MP
3
and MP
4
forming a current mirror are coupled to the first and second transistors MP
1
and MP
2
, respectively, in parallel. The buffer enable signal buffer_en is applied to the gates of the third and fourth PMOS transistors MP
3
and MP
4
.
The inverter
11
B includes a pull-up PMOS transistor MP
5
and a pull-down NMOS transistor MN
4
. An output signal of the differential amplifier
11
A is commonly applied to the gates of the pull-up PMOS transistor MP
5
and a pull-down transistor MN
4
.
FIG. 3
is a circuit diagram illustrating the internal buffer
12
in FIG.
1
. The internal buffer
12
includes a first inverter INV
1
and a second inverter INV
2
coupled in series. The number of the inverters in the internal buffer
12
may be adjusted.
For example, an operation of the input buffer of the differential amplification type will be described by referring to
FIGS. 2 and 3
. When the input signal IN is applied to an input terminal of the differential amplifier
11
A, the differential amplifier
11
A will be operated according to states whether the voltage level of the input signal IN is higher or lower than that of the reference voltage signal Vref because since the voltage of the input signal IN is higher or lower than the reference voltage signal Vref. The reference voltage signal Vref is a static voltage, which always maintains a constant voltage level. The reference voltage signal Vref may be provided through a specific input pin from an external circuit or may be generated in the semiconductor device.
A constant current I
1
flows at the first NMOS transistor MN
1
receiving the reference voltage signal Vref. A current flowing at the second NMOS transistor MN
2
, which is symmetrically configured with the first NMOS transistor MN
1
, is determined by the voltage level of the input signal IN. In particular, the differential amplifier
11
A determines a voltage level of an output node N
1
according to a comparison result between the currents I
1
and I
2
.
If the current I
2
is relatively higher than the current I
1
, the voltage level of the output node N
1
decreases. Finally, a signal of a logic high level is outputted via the inverter
11
B. In this case, the input buffer
100
issues a signal of a logic high level. On the other hand, if the current I
2
is relatively lower than the current I
1
, an output of the inverter
11
B becomes a signal having a logic low level. In this case, the input buffer issues a signal of a logic low level. The buffer enable signal buffer_en is disabled to a logic low level at a power-down mode or a self-refresh mode so that the input buffer is inactivated to a precharge state and, in other modes, the buffer enable signal buffer_en is adjusted to a logic high level so that the input buffer is activated.
The input buffer
100
basically plays a role of an interface for transmitting signals between an internal circuit and an external circuit of a semiconductor device. Therefore, an input buffer configured to rapidly transmit signal variation at an input terminal is required. The semiconductor device performing an amplification operation with high gain is suggested to rapidly transmit signals.
Because the reference voltage signal Vref having a constant potential level is always supplied to the gate of the first NMOS transistor MN
1
in the input buffer
100
of the differential amplification type illustrated in
FIGS. 1
to
3
, the current I
1
flowing at the first NMOS transistor MN
1
is fixed. Therefore, high amplitude of the input signal IN is required for a rapid operation. Generally, however, small amplitude of an input signal is required to improve signal integration and rapidly vary a voltage level of a signal in a system operated with a high speed.
SUMMARY OF THE DISCLOSURE
An input buffer of a differential amplification type and a method for improving a signal transmission speed without increase of amplitude of an input signal are described herein. An input buffer for buffering an input signal to provide an internal signal in a semiconductor device includes: a reference voltage adjusting unit configured to receive a reference voltage and to output a first reference signal having a potential level higher than that of the reference voltage and a second reference signal having a potential level lower than that of the reference voltage; a multiplexing unit configured to selectively output one of the first and second reference signals as a newly selected reference signal in response to the internal signal; a differential amplification unit confi
Hynix / Semiconductor Inc.
Le Don
Marshall & Gerstein & Borun LLP
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