Input buffer of a semiconductor device that gives only a...

Details Input buffer of a semiconductor device that gives only a... Input buffer of a semiconductor device that gives only a...

2001-04-30

2002-10-29

Lee, Michael G. (Department: 2876)

Electronic digital logic circuitry

Interface

Current driving

C326S080000, C326S068000, C326S086000, C365S235000

Reexamination Certificate

active

06472907

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input buffer of a semiconductor device, and in particular to an input buffer of a semiconductor device that generates an internal signal in response to an external signal and gives the internal signal to its internal circuit.
2. Description of the Background Art
FIG. 8
is a block diagram showing a conventional semiconductor memory device. In
FIG. 8
, this device has a control signal buffer
51
, an address buffer
52
, a clock buffer
53
, a data output buffer
54
and a data input buffer
55
.
The control signal buffer
51
transmits an external control signal CNT including a plural-bit signal to an internal circuit
56
. By the external control signal CNT, various commands such as a read command and a write command are given to the internal circuit
56
.
The address buffer
52
transmits an external address signal ADD including a plural-bit signal to the internal circuit
56
. The internal circuit
56
includes memory cells, each of which a specific address is assigned to. By the external address signal ADD, any one of the memory cells is designated. The clock buffer
53
synchronizes with external clock signals CLK and /CLT to generate a signal for designating output timing of data and then give the signal to the internal circuit
56
.
In response to a read command, the internal circuit
56
reads data in the memory cell designated by the external address signal ADD. In response to the signal from the clock buffer
53
, the read data DO is outputted through the data output buffer
54
to the outside. Write data DI is given through the data input buffer
55
to the internal circuit
56
. In response to a write command, the internal circuit
56
writes the data DI in the memory cell designated by the external address signal ADD.
FIG. 9
is a circuit diagram of the clock buffer
53
. In
FIG. 9
, the clock buffer
53
includes P channel MOS transistors
61
and
62
, and N channel MOS transistors
63
and
64
. The MOS transistors
61
-
64
constitute a comparator for comparing the clock signal CLK with the clock signal /CLK complementary thereto so as to output a signal VO having a level corresponding to the result of the comparison.
In the case that the level of the clock signal CLK is lower than that of the clock signal /CLK, the electric current flowing through the MOS transistors
61
-
63
becomes smaller than that flowing through the MOS transistor
64
so that the signal VO is at an “L” level. In the case that the level of the clock signal CLK is higher than that of the clock signal /CLK, the electric current flowing through the MOS transistors
61
-
63
becomes larger than that flowing through the MOS transistor
64
so that the signal VO is at an “H” level. When the clock signal CLK is raised up from the “L” level (ground potential GND) to the “H” level (power source VCC) and the clock signal /CLK is fallen down from the “H” level to the “L” level, the signal VO is raised from the “L” level to the “H” level. The read data DI is outputted through the data output buffer
54
to the outside, in synchronization with the rising edge of the signal VO.
FIG. 10
is a circuit diagram of the data input buffer
55
. In
FIG. 10
, the data input buffer
55
includes P channel MOS transistors
71
and
72
, N channel MOS transistors
73
and
74
, and an inverter
75
. The MOS transistors
71
-
74
and the inverter
75
constitute a comparator for comparing the level of the external data signal DI with a reference potential VR (VCC/2) to output a signal VO corresponding to the result of the comparison.
In the case that the level of the data signal DI is lower than the reference potential VR, the electric current flowing through the MOS transistor
74
becomes smaller than that flowing through the MOS transistors
71
-
73
so that the signal VO is at the “L” level. In the case that the level of the data signal DI is higher than the reference potential VR, the electric current flowing through the MOS transistor
74
becomes larger than that flowing through the MOS transistors
71
-
73
so that the signal VO is at the “H” level. The signal VO is written in the selected memory cell in the external circuit
56
.
However, such a conventional semiconductor memory device has the following problem.
FIGS. 11A and 11B
are timing charts showing operation of the clock buffer
53
shown in FIG.
9
. The clock signal CLK is raised up from the “L” level to the “H” level and the clock signal /CLK is fallen down from the “H” level to the “L” level, so that the signal VO is raised up from the “L” level to the “H” level at the cross point where the clock signals CLK and /CLK cross each other. In this case, the response time for the rise from the “L” level of the signal VO to the midpoint level (VCC/2) thereof, which starts correspondingly to the cross point, varies dependently on the level of the cross point.
Specifically, the response time &Dgr;t
1
in the case that the level of the cross point is higher than VCC/2 (
FIG. 11A
) is shorter than the response time &Dgr;t
2
in the case that the level of the cross point is lower than VCC/2 (FIG.
11
B). This is based on the following reason. As shown in
FIG. 12
, electric current I flowing through the N channel MOS transistors
63
and
64
is not in proportion to input potential VI (the level of the clock signals CLK and /CLK). Thus, when the input potential VI of the N channel MOS transistors
63
and
64
is high, the ratio of electric current variation &Dgr;I
1
to potential variation &Dgr;V
1
(i.e., &Dgr;I
1
/ &Dgr;V
1
) is relatively large. On the other hand, when the input potential VI of the N channel MOS transistors
63
and
64
is low, the ratio of electric current variation &Dgr;I
2
to potential variation &Dgr;V
2
(i.e., &Dgr;I
2
/ &Dgr;V
2
) is relatively small.
As described above, in conventional semiconductor memory devices, the response time of the signal VO, which starts correspondingly to the cross point of the clock signals CLK and /CLK, is scattered. Therefore, access time is also scattered so that the operation of the semiconductor memory devices is disturbed from being made speedy.
FIGS. 13
A and B are time charts of the data input buffer
55
shown in FIG.
10
. The data signal DI is raised up from the “L” level to the “H” level, so that the signal VO is raised up from the “L” level to the “H” level at the cross point where the data signal DI and the reference potential VR cross each other. The data signal DI is fallen down from the “H” level to the “L” level, so that the signal VO is fallen down from the “H” level to the “L” level at the cross point where the data signal DI and the reference potential VR cross. In this case, the response time &Dgr;tH for the rise from the “L” level of the signal VO to the midpoint level thereof, which starts correspondingly to the cross point, is shorter than the response time &Dgr;tL for the fall from the “H” level of the signal VO to the midpoint level thereof, which starts correspondingly to the cross point.
This is based on the following reason. As shown in
FIG. 14
, electric current I flowing through the N channel transistor
74
is not in proportion to input potential VI (the level of the data signal DI). Thus, when the input potential VI of the N channel MOS transistor
74
is higher than the reference potential VR, the ratio of electric current variation &Dgr;IH to potential variation &Dgr;VH (i.e., &Dgr;IH/ &Dgr;VH) is relatively large. On the other hand, when the input potential VI of the N channel MOS transistor
74
is lower than the reference potential VR, the ratio of electric current variation &Dgr;IL to potential variation &Dgr;VL (i.e., &Dgr;IL/&Dgr;VL) is relatively small.
As described above, in conventional semiconductor memory devices, the response time of the signal VO in response to the external data signal DI is scattered. Therefore, long setup time and holding time are necessary. Thus, the operation of the semiconductor memory devices is disturbed from being made speedy.
SUM

Affiliated with

Also associated with

Rating

Input buffer of a semiconductor device that gives only a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input buffer of a semiconductor device that gives only a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input buffer of a semiconductor device that gives only a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2950524