Input buffer means for high voltage operation

Details Input buffer means for high voltage operation Input buffer means for high voltage operation

1999-04-12

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S086000, C326S081000

Reexamination Certificate

active

06320416

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an input buffer means for high voltage operation, and more particularly, to an input buffer means of a semiconductor memory device, which achieves noise margin and satisfactory performance at a required speed by incorporating a transmission gate.
BACKGROUND OF THE INVENTION
The semiconductor memory integrated circuit, for example, the dynamic random, access memory (DRAM), generally adopts input buffer means at the input end of the address latch for buffering the input address signal. The address latch is provided with the input buffer to obtain sufficient noise margin for rejecting noise, and fast processing speed. Moreover, the input buffer should ensure the normal function of the address latch and the reliability thereof in case of an input signal having excessive voltage. In other words, the function of the input buffer means is to ensure the performance of the address latch for high-voltage and high-speed input signals.
The conventional input buffer means is generally connected to an external voltage source E
VCC
to increase the allowable range of input signal levels.
FIG. 1
shows the block diagram of a conventional input buffer means for an address latch in a semiconductor memory integrated circuit. As shown in this figure, the input buffer has input terminal to receive the input address signal, an output terminal to send the latched address signal. Moreover, the an input buffer means is connected to an external voltage source to prevent malfunction in case of input signal having excessive level.
However, in the above-mentioned input buffer, the processing speed and the signal robustness is degraded when the voltage level of the external voltage source E
VCC
is reduced, for example, from 5V to 3V. Moreover, the output high level V
OH
and the noise margin of the input buffer
1
is also degraded such that the output signal thereof may be at a wrong level with respect to next stage circuit.
SUMMARY OF THE INVENTION
The present invention is intended to solve the above problems by providing an input buffer means which has required immunity to the noise of the external voltage source, and outputs a signal with a definite level for the next stage. In another aspect of the invention, the inventive input buffer can be employed in high-speed applications, such as fast page mode operation. Therefore, the inventive input buffer can be advantageously adopted in DRAM design.
It is an object of the present invention to provide an input buffer means for high voltage operation, which can enhance noise margin and sustain a definite V
OH
even though the voltage of the external voltage source is reduced.
It is another object of the present invention to provide an input buffer for a high speed input signal such that the processing speed will not be degraded even though the voltage of the external voltage source is reduced.
To achieve the above and other objects, the present invention provides an input buffer means having a transmission gate and is suitable for application of a address latch with a wide input signal level. The address latch adopting the inventive input buffer means further comprises a control latch for latching the address data, a reference circuit for providing a reference voltage, and a first and a second output control circuit to drive circuit of next stage.
The transmission gate of the inventive input buffer is preferably connected to a boosting voltage source such that the address latch or other digital circuit equipped with the inventive input buffer has fast processing speed and the capability of high voltage operation, and will not have degraded noise margin when the voltage of the external voltage source is reduced. It should be pointed out that the boosting voltage generator is known to those skilled in the related art, and thus the detailed description thereof is omitted here for clarity.
The transmission gate of the inventive input buffer means is preferably in an inverter-type circuit, wherein the transmission gate is connected to the input terminal of an inverter, and then the output of the inverter is sent to the inverter-type address latch or other digital circuit. Therefore, the inventive input buffer can also achieve the above objects for an inverter-type address latch.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:


REFERENCES:
patent: 4656373 (1987-04-01), Plus
patent: 5414312 (1995-05-01), Wong
patent: 5448198 (1995-09-01), Toyashima et al.
patent: 5673277 (1997-09-01), Amitai et al.
patent: 5764077 (1998-06-01), Andresen et al.
patent: 6025737 (2000-02-01), Patel et al.

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