Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-06-11
2001-07-10
Ton, Dang (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S235000
Reexamination Certificate
active
06259698
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C §119 from an application entitled An Input Buffer Controller Using Back-Pressure Signals In ATM Switches And A Method For Determining The Logical Queue Depth earlier filed in the Korean Industrial Property Office on Jun. 11, 1997, and there duly assigned Serial No. 97-24145 by that Office.
FIELD OF THE INVENTION
The present invention relates to an Input Buffer Controller of switching system of input buffering type that controls the cell-input to the switching system using the back-pressure signal. More particularly, the invention is intended to improve the cell loss probability that may occur in each input buffer by dynamically changing the logical queue size within the input buffer using the back-pressure signal from the switch fabric and the logical queue depth, that is, it is intended to provide an input buffer controller using back-pressure signals in the asynchronous transfer mode (ATM) switch and an algorithm for determining the logical queue size.
DESCRIPTION OF THE RELATED ART
With the increasing needs for large transfer capacity and high speed transmission of digital data communication network systems, such as the broadband integrated services digital network (BISDN), the development of a more efficient data-transfer routing scheme for such network systems has been in demand. In recent years, as one of the BISDN systems satisfying the requirements, attention is paid to a specific digital data network system that employs a specific packet-oriented data-transfer mode which uses asynchronous time division multiplexing techniques, which is called the asynchronous transfer mode (ATM). ATM is a dedicated-connection switching technology that organizes digital data into 53 byte cells, or packets, and transmits them over a medium using digital signal technology. Individually, a cell is processed asynchronously relative to other related cells and is queued before being multiplexed over the line. Along with SONET (Synchronous Optical Network) and several other technologies, ATM is a key component of BISDN.
The details of the data transmission principles in the ATM communication network system have been described in several recommendations as published by the international telegraph and telephone consultative committee (CCITT).
More specifically, with the ATM network, the multiplexed information flow to be communicated between the sender and receiver terminals is organized into a plurality of cells of fixed size. In ATM switching facilities it is frequently necessary to switch data cells from several input lines to one and the same output line. This is one of the reasons why data cells are temporarily stored before, during, or after the switching process. The temporary storage may be in the form of several parallel queues. The queues are treated by a priority relationship known as priority classes, so that the data cells are served differently according to which queue they belong to.
An ATM switch distinguishes itself from a circuit switch in that it must reconfigure itself essentially every cell period. Furthermore, it must deal with a cell stream from each of its input ports wherein each cell may be destined for a different output port. This leads to contention among cells for output ports, since it is entirely possible for cells from two input ports to be destined for the same output port at the same time. This implies the need for storage somewhere in the switch so that all cells can eventually reach their intended output port.
In many architectures, contention that occurs for an output port means that some portion of the switch is idle while a cell waits, implying degradation in the throughput of the switch. Because of the statistical nature of the arrivals of cells at the input ports and of the destinations, there usually exists some probability of cell loss, which must be minimized. Finally, even if there is no cell loss, periods of considerable contention lead to large numbers of cells being instructed to wait somewhere in the storage media of the switch, implying long delays through the switch for some cells some of the time, leading to variations in transport delay or cell jitter. The following references, incorporated by reference, describe some known ATM system architectures: U.S. Pat. No. 5,367,520 to Robert R. Cordell entitled Method And System For Routing Cells In An ATM Switch; U.S. Pat. No. 5,440,547 to Hiroshi Easki et al. entitled Data-Transfer Routing Management For Packet-Oriented Digital Communication System Including ATM Networks; U.S. Pat. No. 5,453,980 to Robertus J. Van Engelshoven entitled Communication Network And Computer Network Server And INterface Modules Used Therein; U.S. Pat. No. 5,521,923 to Gert Willmann et al. entitled Method And Facility For Temporarily Storing Data Packets, And Exchange With Such Facility; U.S. Pat. No. 5,530,806 to Joseph H. Condon et al. entitled Method And Apparatus For Storing And Retrieving Routing Information In A Network Node; U.S. Pat. No. 5,570,348 to Brian D. Holden entitled Method And Apparatus For Enqueueing Data Cells In An ATM Switch Fabric Architecture; U.S. Pat. No. 5,583,861 to Brian D. Holden entitled ATM Switching Element And Method Having Independently Accessible Cell Memories; and U.S. Pat. No. 5,704,047 to Stefan Schneeberger entitled ATM Communication System herein Upstream Switching Element Stops The Transmission Of Message For A Predetermined Period Of Time Upon Backpressure Signal.
In view of the foregoing references, a simple ATM switch can be constructed by preceding a crosspoint array with a FIFO (first-in-first-out) input buffer on each of its input ports. A contention resolution device then examines all of the output port requests, comparing them against one another, and decides which FIFOs may empty a cell into the switch core, permitting only one cell to be routed to any given output port. Cells that contend and lose will get a chance to leave their FIFO during the next cell period. If none of these input buffers overflows, then there will be no cell loss. A losing contender at the head of one of these queues or lines forces all cells behind it to wait, even if they are destined for an output port that is free.
This type of architecture is called an input buffered switch. A system architecture of a N×N input buffer switching system using a method of input buffering includes a routing table element attaching a routing tag to an ATM input cell using the information of the output port, an input buffer storing the cells being input and a switching fabric having a cell-transmission function between an input port and an output port using the routing tag. A routing table element and an input buffer are required, at a one to one relationship, for every input port and the switching fabric may be comprised of a unit switch or several unit switches.
The cells being input to the switching system, above all, are sent to routing table element, and the routing table element directs the storage of the input cell to the appropriate logical queue within the input buffer according to the class of the input cell. In the switch system, the input buffer is split into a plurality of logical queues to support a plurality of priorities.
The method for transmitting a cell in the logical queues to the routing table element is such that the method checks first in the logical queues if a cell is stored from the logical queue having the highest priority one after another. If there is a cell to be transmitted in the logical queue that has been checked, it checks if there is a back-pressure signal corresponding to the checked logical queue.
The switch fabric has a table that stores the priority of the cell, which is in the shared buffer, and the number of each of the priority cells for each input port. If the cells having the same priorities are transmitted to the same input ports, a collision may happen between the cells having the same priorities and the same input ports. So, a back-
Byun Sung-Hyuk
Heo Jeong-Won
Lee Ju-Yong
Lee Kyung-Geun
Shin Jae-Jin
Bushnell , Esq. Robert E.
Sam Phirin
Samsung Electronics Co,. Ltd.
Ton Dang
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