Input buffer circuit for transforming pseudo differential...

Details Input buffer circuit for transforming pseudo differential... Input buffer circuit for transforming pseudo differential...

2001-07-06

2002-09-24

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000, C327S077000

Reexamination Certificate

active

06456122

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to an input buffer circuit employed for a memory or a data processing system.
2. Description of the Related Art
An input buffer circuit forms an input portion of a differential comparator, and the differential comparator has the functions of sampling a difference between two input signals during a specific clock period, and storing/transmitting the difference value. If the input buffer circuit of the differential comparator is used for a memory, the input signals are from a flash cell and a reference cell, and the output signals are fed to a differential input latch, which is a next stage. If the input buffer circuit is used in a data processing system where analog signals are transformed into digital signals, a difference between a signal which will be transformed, and a processed reference signal is read, and the result is available as an output.
FIG. 1
illustrates a circuit diagram of a circuit for sampling and holding a conventional pseudo differential input. Referring to
FIG. 1
, the conventional circuit includes an input buffer
110
for transmitting a pseudo differential input (Vin and Vref) to a flip-flop
120
which is a next stage; a flip-flop
120
for sampling and holding an output signal of the input buffer
110
; and an output portion
130
that converts an output signal of the flip-flop
120
to a logic level.
The input buffer
110
includes a pull-up current source; 2 PMOS transistors (M
1
and M
2
); a pull-down current source, an NMOS transistor (M
5
); and a differential input portion, NMOS transistors (M
3
and M
4
).
The flip-flop
120
includes NMOS transistors (M
10
and M
11
) for receiving the two output signals from the input buffer, PMOS transistors (M
6
and M
7
) and NMOS transistors (M
8
and M
9
) for sampling and holding signals fed into the two NMOS transistors (M
10
and M
11
), an NMOS transistor (M
12
) for keeping sampling and holding in synchronization with a clock signal (Clk), and a switch (Sw) operated by an inverted clock signal (Clkb).
The output portion
130
includes two inverters (Inv
1
and Inv
2
), PMOS transistors (M
13
, M
14
, M
15
and M
16
) and NMOS transistors (M
17
, M
18
, M
19
and M
20
) for enlarging a swing width of output signals (out and outb) as much as possible.
However, the conventional input buffer circuit
110
described in
FIG. 1
has at least one significant disadvantage. Specifically, the difference between an input signal (Vin) and a reference signal (Vref) is not large, or if there are frequent changes during one period of a clock signal (Clk), output node voltages
11
and
12
of the input buffer circuit
110
may vary.
SUMMARY OF THE INVENTION
To solve the above problems, it is a feature of an embodiment of the present invention to provide an input buffer circuit which transforms pseudo differential input signals into full differential output signals.
Accordingly, to provide the above feature, there is provided an input buffer circuit including a pull-up current source for sourcing an electric current, two pull-down current sources for sinking the sourcing electric current, a differential input portion for receiving differential input signals, and a positive feedback portion for enlarging the differential output voltage.
The pull-up current source is formed of two PMOS transistors, the gates of which are connected to a low voltage power supply (Vss), so that an “on” state is always maintained and an electric current is provided to the differential input portion. It is preferable to make the size of the two transistors in the pull-up current source the same and provide the same amount of electric current to each of two output terminals.
The first pull-down current source and the second pull-down current source are each formed of one NMOS transistor. The gates of the first and second pull down current sources are connected to an external applied power source, a bias voltage, in order to sink an electric current from the pull-up current source in a saturation region. The first pull-down current source and the second pull-down current source sink an electric current flowing from the two PMOS transistors which form the pull-up current source.
The differential input portion is formed of two NMOS transistors, and receives an input signal (Vin) and a reference signal (Vref). An electric current corresponding to the voltage of the two received signals flows from the pull-up current source to the two output terminals of the input buffer circuit, and the amount of the electric current is indicated as a voltage of the respective output terminals.
The positive feedback portion is formed of two NMOS transistors, and when there is a voltage drop across the two output terminals of the input buffer circuit in response to the two input signals (Vin and Vref) applied to the differential input portion, a voltage drop between the two output terminals is enlarged using positive feedback.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.


REFERENCES:
patent: 5526314 (1996-06-01), Kumar
patent: 5625308 (1997-04-01), Matsumoto et al.
patent: 5894233 (1999-04-01), Yoon
patent: 6147514 (2000-11-01), Shiratake

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