Input buffer circuit for RF phase-locked loops

Details Input buffer circuit for RF phase-locked loops Input buffer circuit for RF phase-locked loops

2000-01-12

2002-05-21

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S478000, C327S432000, C327S563000, C327S103000, C327S065000, C326S089000, C326S082000, C330S252000

Reexamination Certificate

active

06392452

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a communication system, and more particularly to an input buffer circuit for radio frequency (RF) phase-locked loops(PLLs).
BACKGROUND OF THE INVENTION
Communication systems for connecting persons to allow them to transmit and receive information back and forth are becoming increasingly powerful. In fact, certain types of systems, such as modems for performing data communication and telephones for performing voice communication, have become indispensable to many users. Generally, communication systems are classified as either wired communication systems which use data transmission lines or wireless communication systems which transmit data using electromagnetic transmissions such as radio frequency (RF) transmissions.
In portable systems that include wireless communication capability, such as pagers, cellular telephones, personal communication service (PCS) phones, personal digital assistants (PDA), and portable computers including laptops and notebook computers, there are several important considerations. These include battery life and, therefore, power consumption, as well as the weight and volume of the system. These factors are all affected by the size and type of integrated circuits that make up the systems in general and their resident communication systems in particular. The size and type of traditionally external components is also an important factor. With the developments made in integrated circuit technology, more and more components which were traditionally considered external components are being embedded in integrated circuits.
FIG. 1
is a block diagram illustrating a conventional communication receiver
100
. Referring to
FIG. 1
, the communication receiver
100
comprises an antenna
1
, a speaker
2
, a radio frequency (RF) amplifier
10
, a mixer
20
, an intermediate frequency (IF) amplifier
30
, a base band analog processor (BBA)
40
, and an RF phase-locked loop (PLL)
95
. The PLL
95
includes a voltage-controlled oscillator VCO
50
, a frequency divider
75
, a phase detector
80
and a filter
90
.
The RF amplifier
10
amplifies an RF signal having radio band frequency received from the antenna
1
. The mixer
20
mixes the RF signal from the RF amplifier
10
with an oscillating signal generated by the VCO
50
to generate an intermediate frequency (IF) signal having intermediate band frequency. The IF amplifier
30
amplifies the IF signal from the mixer
20
. The BBA processor
40
receives the IF signal from the IF amplifier
30
and converts the IF signal to a base band analog (BBA) signal having base band frequency. The BBA signal is provided as an output to the speaker
2
.
Generally, phase-locked loops (PLL) can be classified according to their frequency characteristics as radio frequency (RF) phase-locked loops, such as PLL
95
in
FIG. 1
, and low frequency (LF) PLLs. For example, referring to
FIG. 2
, which is a detailed block diagram illustrating the RF PLL
95
shown in
FIG. 1.
, recent mobile telecommunication systems such as the cellular phone and the PCS phone use an RF PLL
95
having a prescaler
60
as a principal part of their systems. The LF PLL does not require a prescaler, since the LF PLL is operated at low frequency.
Referring to
FIG. 2
, the RF PLL
95
comprises the VCO
50
, the phase detector
80
, the filter
90
and the frequency divider
75
, which includes the prescaler
60
and a divider
70
. In the RF PLL
95
shown in
FIG. 2
, the VCO
50
generates an oscillating signal having the radio band frequency. The frequency divider
75
divides the frequency of the oscillating signal from the VCO
50
by a predetermined divisor, for example, N, and outputs a divided oscillating signal Ffeed to the phase detector
80
. The prescaler
60
is used for pre-dividing the frequency of the oscillating signal from the VCO
50
, and the divider
70
is used for dividing the pre-divided oscillating signal from the prescaler
60
.
The prescaler
60
divides the oscillating signal, typically having a frequency in the Gigahertz (GHz) range, and outputs a pre-divided oscillating signal, typically having a frequency in the tens of Megahertz (MHz), to the divider
70
. The divider
70
divides the pre-divided oscillating signal and outputs a further divided oscillating signal to the phase detector
80
. The prescaler
60
typically includes emitter coupled logic (ECL) circuitry which is applicable for high speed operation.
The phase detector
80
compares a reference input signal Fref having a reference frequency with the divided oscillating signal Ffeed from the frequency divider
75
, to generate a control signal which is applied to the VCO
50
through the filter
90
, so as to control the VCO
50
.
The prescaler
60
composed of the ECL circuitry, comprises an input buffer circuit for amplifying the low-level oscillating signal to the ECL level. The input buffer circuit is capable of operating in the Ghz frequency range and is used to provide a wide input sensitivity to the prescaler
60
. One example of the input buffer circuit for the ECL prescaler is set forth in a paper entitled, “A 3-mW 1.0-Ghz Silicon-ECL Dual-Modulus Prescaler IC”, by Moriaki Mizuno, Hirokazu Suzuki, Masami Ogawa, Kouji Sato, and Hiromich Ichikawa, published in the December, 1992 issue of IEEE JOURNAL OF SOLID STATE CIRCUITS, vol. 27, No. 12, pages 1794-1797.
FIG. 3
is a circuit diagram which illustrates an input buffer circuit
65
included in the prescaler
60
shown in
FIG. 2
, and which is disclosed in the above paper. Referring to
FIG. 3
, the input buffer
65
comprises a first amplifier
61
, a second amplifier
62
, and a output driving circuit
63
. The first amplifier
61
receives an oscillating signal IN and an inverted oscillating signal INB from the VCO
50
. The input signals IN and INB have 50 mV-0.5V of peak voltage, and a high frequency response of more than 1 GHz. Transistors Q
1
, Q
2
, Q
3
and Q
4
are included in the first and the second amplifiers
61
and
62
. They operate as switches when the voltage of the input signal IN is higher than 100 mV, for example, and operate as amplifiers when the voltage of the input signal IN is 50 mV or less, for example. The bandwidths of output signals OUT and OUTB of the input buffer circuit
65
are restricted by parasitic capacitances existing on nodes N
1
, N
2
, N
3
and N
4
, and load resistors RL
1
, RL
2
, RL
3
and RL
4
. The output signals OUT and OUTB are digitized by the switching operation of the transistors Q
1
, Q
2
, Q
3
and Q
4
, and then they are outputted to the phase detector
80
through the output driving circuit
63
.
FIG. 4
is a diagram illustrating simulated output characteristics of the input buffer
65
shown in FIG.
3
. The plot of
FIG. 4
illustrates a characteristic of the input buffer generated by a computer simulation, such as SPICE, with circuit parameters set as follows: VDD=3V, VBB
1
=1.5V, RL
3
=RL
4
=1.75 k&OHgr;, IEE
1
=IEE
2
=200 &mgr;A, and IEE
3
=IEE
4
=50 &mgr;A. The simulated frequency response with this current has adequate gain (for example, 14 dB) up to 1.0 Ghz as shown in FIG.
4
. The output characteristics of the input buffer
65
will be described in detail below, including comparing them with the output characteristics of an input buffer according to an embodiment of the present invention.
To obtain the output characteristics illustrated in
FIG. 4
, switching voltages across load resistors RL
1
, RL
2
, RL
3
and RL
4
must be kept above 300 mV in the input buffer circuit
65
, so as to satisfy the ECL output characteristics. That is, the first and the second switching voltages obtained by multiplying a first switching current IEE
1
and the respective load registers RL
1
and RL
2
must be kept above 300 mV in the first amplifier
61
. Similarly, the third and the fourth switching voltages obtained by multiplying a second switching current IEE
2
and the respective load registers RL
3
and RL
4
must be kept above 300 mV in

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